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Computers, IEEE Transactions on

Issue 9 • Date Sep 1991

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Displaying Results 1 - 14 of 14
  • Express cubes: improving the performance of k-ary n -cube interconnection networks

    Page(s): 1016 - 1023
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    The author discusses express cubes, k-ary n-cube interconnection networks augmented by express channels that provide a short path for nonlocal messages. An express cube combines the logarithmic diameter of a multistage network with the wire-efficiency and ability to exploit locality of a low-dimensional mesh network. The insertion of express channels reduces the network diameter and thus the distance component of network latency. Wire length is increased, allowing networks to operate with latencies that approach the physical speed-of-light limitation rather than being limited by node delays. Express channels increase wire bisection in a manner that allows the bisection to be controlled independently of the choice of radix, dimension, and channel width. By increasing wire bisection to saturate the available wiring media, throughput can be substantially increased. With an express cube both latency and throughput are wire-limited and within a small factor of the physical limit on performance View full abstract»

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  • Redundant CORDIC methods with a constant scale factor for sine and cosine computation

    Page(s): 989 - 995
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    Proposes two redundant CORDIC (coordinate rotation digital computer) methods with a constant scale factor for sine and cosine computation, called the double rotation method and the correcting rotation method. In both methods, the CORDIC is accelerated by the use of a redundant binary number representation, as in the previously proposed redundant CORDIC. In the proposed methods, since the number of rotation-extensions performed for each angle is a constant, the scale factor is a constant independent of the operand. Hence, one does not need to calculate the scale factor during the computation, and can make a more efficient sine and cosine generator than that based on the previous redundant CORDIC View full abstract»

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  • A contention-based bus-control scheme for multiprocessor systems

    Page(s): 1046 - 1053
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    The authors study contention-based bus-control schemes for scheduling processors in using a bit-parallel shared bus. The protocol is designed under the requirements that each processor exhibit a random access behavior, that there be no centralized bus control in the system, and that access be granted in real time. The proposed scheme is based on splitting algorithms used in conventional contention-resolution schemes, and utilizes two-state information obtained from collision detection. Two versions of the bus-control scheme are studied. The static one resolves contentions of N requesting processors in an average of O(logW/2N) iterations, where W is the number of bits in the bit-parallel bus. An adaptive version resolves contentions in an average time that is independent of N View full abstract»

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  • Discrete and continuous models for the performance of reconfigurable multistage systems

    Page(s): 1024 - 1033
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    The authors analyze the performance of multiprocessor systems with a multistage interconnection network in the presence of faulty components. Models for estimating the system performance, as measured by its bandwidth and processing power, are developed for two different modes of operation. In the first mode, the operation of the system is fully synchronized and all processors which require memory access issue their requests simultaneously. In the second, each processor is allowed to issue its request at any time instant. For each of the two modes of operation, two models are presented providing lower and upper estimates for the bandwidth of multistage systems and an upper estimate for their processing power. The operation of 16×16 synchronous and asynchronous reconfigurable systems has been simulated and the bandwidth and processing power have been calculated View full abstract»

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  • Data routing networks for systolic/pipeline realization of prime factor mapping

    Page(s): 1072 - 1074
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    It is pointed out that transformed data computed by systolic/pipeline processors using the data shuffling network recently proposed by T.K. Troung et al. (ibid., vol.37, p.266-73, Mar. 1988) cannot be unscrambled by simply reversing the cyclic row and cyclic column shufflings. This can be amended by the proposed restoration scheme. In addition, efficient architectures for the data routing networks with low circuit complexities are proposed. These form useful building blocks for very-high-throughput hardware realizations View full abstract»

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  • Coping with erroneous information while sorting

    Page(s): 1081 - 1084
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    The authors study the problem of sorting n distinct elements in ascending sequence according to a total order, using comparison queries which receive `yes' or `no' answers, but of which as many as e may be erroneous. In a half-lie version, all `yes' answers are guaranteed to be correct and the errors are confined to `no' answers. It is shown that the comparison query complexity of the sorting problem for this case is Ω(n log n+e), and an asymptotically optimal algorithm is demonstrated. In a full-lie version, both `yes' and `no' answers can be false. It is shown that the comparison query complexity of the sorting problem for this case is Ω(n log n+en) View full abstract»

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  • VLSI architectures for multidimensional transforms

    Page(s): 1053 - 1057
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N×N× . . . ×N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(Nd+2a) and computation time T=O(dNd/2-ab ), and achieve the AT2 bound of AT2=O(n2b 2) for constant d, where n=Nd and O<ad/2 View full abstract»

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  • Analysis and design of linear finite state machines for signature analysis testing

    Page(s): 1034 - 1045
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    The authors present a theoretical investigation of the aliasing error probability (AEP) in signature analysis testing by means of linear finite state machines (LFSMs). The equations of the resulting Markov chain model of the LFSM are solved to determine an exact expression of the AEP as a function of the main LFSM features and of the relevant parameters of the testing environment. This expression is used to prove criteria for the synthesis of LFSMs with minimum asymptotic and transient AEP. A fundamental lower bound on the AEP is presented, which represents the performance limit of any LFSM with respect to aliasing minimization. It is shown that the AEP in machines realizing counters mod 2k-1 is the closest to such a bound, in particular periodically reaching it View full abstract»

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  • Analysis of detection capability of parallel signature analyzers

    Page(s): 1075 - 1081
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    A rigorous mathematical analysis is presented to identify error conditions under which aliasing can occur for several common types of serial signature analyzers (SSAs) and parallel signature analyzers (PSAs). The PSAs are faster and require less hardware than the SSAs; however, for PSAs some double errors are a special cause of concern. Such aliasing errors are analyzed and it is shown that PSA pairs can be identified for which these errors are disjoint. Novel reconfigurable PSA designs are presented which use a two-signature scheme to detect all double errors View full abstract»

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  • On self-routing in Benes and shuffle-exchange networks

    Page(s): 1057 - 1064
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    The authors present self-routing algorithms for realizing the class of linear permutations in various multistage networks such as Benes and 2n-stage shuffle-exchange. Linear permutations are useful in providing fast access of data arrays. In the first half of the network, switches are set by comparing the destination tags at their inputs, and, in the second half, switches are set using the Omega self-routing algorithm. It is shown that the comparison operations can be implemented in bit-serial networks without loss of time. In contrast, with the well-known Benes network self-routing algorithm of D. Nassimi and S. Sahni (1981), switches are set by giving priority to the destination tag at the upper input to them. The algorithms presented are useful in providing fast access of various data patterns using interconnection networks cheaper than crossbars View full abstract»

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  • Pseudorandom rounding for truncated multipliers

    Page(s): 1065 - 1067
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    An economical, unbiased, overflow-free rounding scheme for multiplication of multiple-precision floating-point numbers is proposed. The scheme, called pseudorandom rounding, saves multiplications of lower bits and makes use of statistical properties of bits around the least significant bit of products in order to compensate for truncated parts. The method is deterministic, and inputs are commutable. The validity of the rounding is verified by numerical simulation View full abstract»

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  • Nonblocking broadcast switching networks

    Page(s): 1005 - 1015
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    Results are presented for nonblocking multistage broadcast networks wherein a request from an idle input port to be connected to some set of idle output ports can be satisfied without any disturbance of other broadcast connections already existing in the network. Furthermore, a linear network control algorithm for realizing such a broadcast connection request is given. These results represent the best known explicit constructions with limited numbers of stages relative to both crosspoint and control algorithm complexity. Thus, these networks are highly useful for practical applications involving the movement of and collaboration with voice/video/text/graphics information that require broadcast capability. These networks are also useful for the interconnection of processor and memory units in parallel processing systems View full abstract»

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  • An a priori approach to the evaluation of signature analysis efficiency

    Page(s): 1068 - 1071
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The authors present an evaluation of signature analysis efficiency which does not rely on assumptions about the distribution of the analyzed error sequences. This is achieved through the use of an `a priori randomization' technique, which leads to a choice of LFSRs (linear feedback shift registers) corresponding to randomly chosen irreducible polynomials of a given degree. As it does not make use of assumptions on the error distribution, the proposed evaluation is more pessimistic than the usual ones. In particular, it takes into account the length of the analyzed sequence. However, it can be valuable when the efficiency of signature analysis has to be guaranteed, for highly dependable applications for instance View full abstract»

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  • Hierarchical quorum consensus: a new algorithm for managing replicated data

    Page(s): 996 - 1004
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    A novel algorithm for managing replicated data is presented. The proposed method is based on organizing the copies of an object into a logical, multilevel hierarchy, and extending the quorum consensus algorithm to such an environment. Several properties of the method are derived and optimality conditions are given for minimizing the quorum size. It is shown that, given a collection of n copies of an object, the method allows a quorum to be formed with n0.63 copies versus [(n+1)/2] copies in the case of the majority voting algorithm. Tradeoffs between the proposed method and three other quorum-based methods are discussed, and the main features of each method are highlighted View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Albert Y. Zomaya
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albert.zomaya@sydney.edu.au