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# IEEE Transactions on Computers

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Displaying Results 1 - 14 of 14
• ### Nonblocking broadcast switching networks

Publication Year: 1991, Page(s):1005 - 1015
Cited by:  Papers (114)  |  Patents (14)
| | PDF (1004 KB)

Results are presented for nonblocking multistage broadcast networks wherein a request from an idle input port to be connected to some set of idle output ports can be satisfied without any disturbance of other broadcast connections already existing in the network. Furthermore, a linear network control algorithm for realizing such a broadcast connection request is given. These results represent the ... View full abstract»

• ### Hierarchical quorum consensus: a new algorithm for managing replicated data

Publication Year: 1991, Page(s):996 - 1004
Cited by:  Papers (114)  |  Patents (3)
| | PDF (672 KB)

A novel algorithm for managing replicated data is presented. The proposed method is based on organizing the copies of an object into a logical, multilevel hierarchy, and extending the quorum consensus algorithm to such an environment. Several properties of the method are derived and optimality conditions are given for minimizing the quorum size. It is shown that, given a collection of n c... View full abstract»

• ### Redundant CORDIC methods with a constant scale factor for sine and cosine computation

Publication Year: 1991, Page(s):989 - 995
Cited by:  Papers (131)  |  Patents (3)
| | PDF (580 KB)

Proposes two redundant CORDIC (coordinate rotation digital computer) methods with a constant scale factor for sine and cosine computation, called the double rotation method and the correcting rotation method. In both methods, the CORDIC is accelerated by the use of a redundant binary number representation, as in the previously proposed redundant CORDIC. In the proposed methods, since the number of... View full abstract»

• ### Analysis of detection capability of parallel signature analyzers

Publication Year: 1991, Page(s):1075 - 1081
Cited by:  Papers (1)  |  Patents (1)
| | PDF (428 KB)

A rigorous mathematical analysis is presented to identify error conditions under which aliasing can occur for several common types of serial signature analyzers (SSAs) and parallel signature analyzers (PSAs). The PSAs are faster and require less hardware than the SSAs; however, for PSAs some double errors are a special cause of concern. Such aliasing errors are analyzed and it is shown that PSA pa... View full abstract»

• ### Analysis and design of linear finite state machines for signature analysis testing

Publication Year: 1991, Page(s):1034 - 1045
Cited by:  Papers (25)
| | PDF (984 KB)

The authors present a theoretical investigation of the aliasing error probability (AEP) in signature analysis testing by means of linear finite state machines (LFSMs). The equations of the resulting Markov chain model of the LFSM are solved to determine an exact expression of the AEP as a function of the main LFSM features and of the relevant parameters of the testing environment. This expression ... View full abstract»

• ### Data routing networks for systolic/pipeline realization of prime factor mapping

Publication Year: 1991, Page(s):1072 - 1074
Cited by:  Papers (4)
| | PDF (180 KB)

It is pointed out that transformed data computed by systolic/pipeline processors using the data shuffling network recently proposed by T.K. Troung et al. (ibid., vol.37, p.266-73, Mar. 1988) cannot be unscrambled by simply reversing the cyclic row and cyclic column shufflings. This can be amended by the proposed restoration scheme. In addition, efficient architectures for the data routing networks... View full abstract»

• ### A contention-based bus-control scheme for multiprocessor systems

Publication Year: 1991, Page(s):1046 - 1053
Cited by:  Papers (1)
| | PDF (812 KB)

The authors study contention-based bus-control schemes for scheduling processors in using a bit-parallel shared bus. The protocol is designed under the requirements that each processor exhibit a random access behavior, that there be no centralized bus control in the system, and that access be granted in real time. The proposed scheme is based on splitting algorithms used in conventional contention... View full abstract»

• ### Discrete and continuous models for the performance of reconfigurable multistage systems

Publication Year: 1991, Page(s):1024 - 1033
Cited by:  Papers (2)
| | PDF (864 KB)

The authors analyze the performance of multiprocessor systems with a multistage interconnection network in the presence of faulty components. Models for estimating the system performance, as measured by its bandwidth and processing power, are developed for two different modes of operation. In the first mode, the operation of the system is fully synchronized and all processors which require memory ... View full abstract»

• ### On self-routing in Benes and shuffle-exchange networks

Publication Year: 1991, Page(s):1057 - 1064
Cited by:  Papers (23)  |  Patents (2)
| | PDF (784 KB)

The authors present self-routing algorithms for realizing the class of linear permutations in various multistage networks such as Benes and 2n-stage shuffle-exchange. Linear permutations are useful in providing fast access of data arrays. In the first half of the network, switches are set by comparing the destination tags at their inputs, and, in the second half, switches are set using th... View full abstract»

• ### An a priori approach to the evaluation of signature analysis efficiency

Publication Year: 1991, Page(s):1068 - 1071
Cited by:  Patents (3)
| | PDF (392 KB)

The authors present an evaluation of signature analysis efficiency which does not rely on assumptions about the distribution of the analyzed error sequences. This is achieved through the use of an a priori randomization' technique, which leads to a choice of LFSRs (linear feedback shift registers) corresponding to randomly chosen irreducible polynomials of a given degree. As it does not make use ... View full abstract»

• ### Coping with erroneous information while sorting

Publication Year: 1991, Page(s):1081 - 1084
Cited by:  Papers (8)
| | PDF (388 KB)

The authors study the problem of sorting n distinct elements in ascending sequence according to a total order, using comparison queries which receive yes' or no' answers, but of which as many as e may be erroneous. In a half-lie version, all yes' answers are guaranteed to be correct and the errors are confined to `no' answers. It is shown that the comparison query complexity o... View full abstract»

• ### VLSI architectures for multidimensional transforms

Publication Year: 1991, Page(s):1053 - 1057
Cited by:  Papers (7)
| | PDF (436 KB)

The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N×N× . . . ×N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(Nd+2a) and computation time T=O(dN... View full abstract»

• ### Pseudorandom rounding for truncated multipliers

Publication Year: 1991, Page(s):1065 - 1067
Cited by:  Papers (6)
| | PDF (232 KB)

An economical, unbiased, overflow-free rounding scheme for multiplication of multiple-precision floating-point numbers is proposed. The scheme, called pseudorandom rounding, saves multiplications of lower bits and makes use of statistical properties of bits around the least significant bit of products in order to compensate for truncated parts. The method is deterministic, and inputs are commutabl... View full abstract»

• ### Express cubes: improving the performance of k-ary n -cube interconnection networks

Publication Year: 1991, Page(s):1016 - 1023
Cited by:  Papers (97)  |  Patents (6)
| | PDF (740 KB)

The author discusses express cubes, k-ary n-cube interconnection networks augmented by express channels that provide a short path for nonlocal messages. An express cube combines the logarithmic diameter of a multistage network with the wire-efficiency and ability to exploit locality of a low-dimensional mesh network. The insertion of express channels reduces the network diameter ... View full abstract»

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org