IEEE Transactions on Computers

Issue 8 • Aug 1991

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Displaying Results 1 - 8 of 8
  • Simplicity versus accuracy in a model of cache coherency overhead

    Publication Year: 1991, Page(s):893 - 906
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1360 KB)

    The important factors building a model of coherency overhead for a single-bus, shared memory multiprocessor are analyzed. Three architectural features are examined: the size of the coherency block, the cache size, and the type of bus operation used to carry out a particular coherency function. The experiments judge the effect of each architectural parameter on model accuracy by selectively includi... View full abstract»

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  • Comprehensive testing of multistage interconnection networks

    Publication Year: 1991, Page(s):935 - 951
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1560 KB)

    The authors present efficient methods for testing packet-switched multistage interconnection networks. In addition to testing the data paths and routing capabilities, tests for detecting faults in the control circuitry including the conflict resolution capabilities are provided. Using a general model of the switch, testing sequences are constructed for the internal functions of the f&time... View full abstract»

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  • Algorithmic synthesis of MVL functions for CCD implementation

    Publication Year: 1991, Page(s):977 - 986
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    Algorithms for synthesis of four-valued one- and two-variable functions for CCD (charge coupled device) implementation are proposed. One-variable synthesis is based on the observation that the cost of a realization of a function f(x) increases in the presence of breaks, or negative transitions, in the value of f as x increases. The function is decomposed to mini... View full abstract»

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  • Disk allocation methods using error correcting codes

    Publication Year: 1991, Page(s):907 - 914
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The problem of declustering, that is, how to distribute a binary Cartesian product file on multiple disks to maximize the parallelism for partial match queries, is examined. Cartesian product files appear as a result of some secondary key access methods. For the binary case, the problem is reduced to grouping the 2n binary strings on n bits in m groups of unsimilar st... View full abstract»

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  • A hybrid number system processor with geometric and complex arithmetic capabilities

    Publication Year: 1991, Page(s):952 - 962
    Cited by:  Papers (24)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    The architecture, design, and performance of a hybrid number system processor are described. The processor performs multiplication, division, square root, and square in the logarithmic number system (LNS) domain. However, the input, output, addition, and subtraction are all executed in the 32-b IEEE standard floating-point number system. With the LNS multiplier and pipelined architecture, the proc... View full abstract»

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  • A note on t-unidirectional error correcting and d(dt)-unidirectional error detecting ( t-UEC and d-UED) codes

    Publication Year: 1991, Page(s):987 - 988
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    Necessary and sufficient conditions for t-unidirectional error correcting and d-unidirectional error detecting (t -UEC and d-UED) codes are shown. In addition, an error in a theorem previously published on t-UEC and d-UED codes (see D.J. Lin and B. Bose, IEEE Trans. Comput., vol.37, p.433-39, Apr. 1988) is corrected View full abstract»

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  • Distributed instruction set computer architecture

    Publication Year: 1991, Page(s):915 - 934
    Cited by:  Papers (4)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1416 KB)

    The Distributed Instruction Set Computer Architecture (DISC) is proposed as a fine-grained multiprocessing computer architecture. DISC uses a parallel instruction set and a distributed control mechanism to explore fine-grained, parallel processing in a multiple-functional-unit system. Multiple instructions are executed in parallel and/or out of order at the highest speed of n instructions... View full abstract»

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  • Design and analysis of master/slave multiprocessors

    Publication Year: 1991, Page(s):963 - 976
    Cited by:  Papers (3)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1096 KB)

    A simple model of master/slave processors is presented, along with two simple, practical scheduling algorithms. An approximate analysis of the model yields simple formulas for performance measures in terms of the hardware and workload parameters, and gives insight into the power and the limitations of master/slave systems. In particular, formulae are obtained for the maximal processing power (thro... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org