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IEEE Transactions on Computers

Issue 7 • Date Jul 1991

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Displaying Results 1 - 12 of 12
  • A VLSI modulo m multiplier

    Publication Year: 1991, Page(s):873 - 878
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROM-based structures is also ... View full abstract»

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  • A real-time locking protocol

    Publication Year: 1991, Page(s):793 - 800
    Cited by:  Papers (54)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    The authors examine a priority driven two-phase lock protocol called the read/write priority ceiling protocol. It is shown that this protocol leads to freedom from mutual deadlock. In addition, a high-priority transactions can be blocked by lower priority transactions for at most the duration of a single embedded transaction. These properties can be used by schedulability analysis to guarantee tha... View full abstract»

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  • I/O overhead and parallel VLSI architectures for lattice computations

    Publication Year: 1991, Page(s):843 - 852
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    The authors introduce input/output (I/O) overhead ψ as a complexity measure for VLSI implementations of two-dimensional lattice computations of the type arising in the simulation of physical systems. It is shown by pebbling arguments that ψ=Ω(n-1 ) when there are n2 processing elements available. If the results must be observed at every generat... View full abstract»

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  • Parallel algorithms for image processing on OMC

    Publication Year: 1991, Page(s):827 - 833
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    The author studies a class of VLSI organizations with optical interconnects for fast solutions to several image processing tasks. The organization and operation of these architectures are based on a generic model called OMC, which is used to understand the computational limits in using free space optics in VLSI parallel processing systems. The relationships between OMC and shared memory models are... View full abstract»

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  • Performance analysis of multiple bus interconnection networks with hierarchical requesting model

    Publication Year: 1991, Page(s):834 - 842
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    The authors study the performance of multiprocessor systems employing multiple buses as the interconnection networks under a nonuniform requesting model, called the hierarchical requesting model. The effective memory bandwidth is chosen as the performance measure. The networks investigated include multiple bus networks with full bus-memory connection, multiple bus networks with single bus-memory c... View full abstract»

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  • The formal description and verification of hardware timing

    Publication Year: 1991, Page(s):811 - 826
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1356 KB)

    A formalism in which timing properties of digital hardware may be specified, derived, and formally verified is introduced as a rigorous theory for hardware timing. A rigorous modeling framework has been used to create a family of related verification techniques rather than a single timing analysis tool. This framework is based on a model of interacting finite state machines called CIRCAL, a formal... View full abstract»

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  • Load balancing in a hybrid ATPG environment

    Publication Year: 1991, Page(s):878 - 882
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The problem of balancing the computational load between fault simulation and conventional ATPG (automatic test program generation) is treated. A rule for switching from probabilistic to deterministic test pattern computation is derived. The criterion is based on a model of monitoring of the simulation process and on an online estimation of the fault detection probabilities. Using these probabiliti... View full abstract»

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  • Aliasing probabilities for feedback signature compression of test data

    Publication Year: 1991, Page(s):867 - 873
    Cited by:  Papers (10)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    A computationally efficient Markov state space model is developed for determining the aliasing probability of a linear feedback shift register when used for test data reduction. The model studied can be used to test data errors which have a constant of probability of error, correlated or repeated use errors, or time varying error probability. Based on a number of simulations of various error model... View full abstract»

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  • A modular fault-tolerant binary tree architecture with short links

    Publication Year: 1991, Page(s):882 - 890
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for m... View full abstract»

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  • Translation of the problem of complete test set generation to pseudo-Boolean programming

    Publication Year: 1991, Page(s):864 - 867
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    An attempt is made to demonstrate that the problem of complete test set generation is amenable to the problem of pseudo-Boolean programming. For this purpose, various types of faults, viz., single faults, multiple faults, and bridging faults, are considered. The key issue is to obtain logical expressions for the primary output line in terms of different faulty internal nodes to find real transform... View full abstract»

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  • Embedding complete binary trees into butterfly networks

    Publication Year: 1991, Page(s):853 - 863
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    The authors present embeddings of complete binary trees into butterfly networks with or without wrap-around connections. Let m be an even integer and q=m+[log m]-1. The authors show how to embed a 2q+1-1-node complete binary tree T(q) into a (m+1)2m+1-node wrap-around butterfly Bw(m+1... View full abstract»

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  • Asynchronous disk interleaving: approximating access delays

    Publication Year: 1991, Page(s):801 - 810
    Cited by:  Papers (21)  |  Patents (58)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    The performance implications of asynchronous disk interleaving are examined. In an asynchronous system, adjacent subblocks are placed independently of each other. Since each of the disks in such a system is treated independently while being accessed as a group, the access delay of a request for a data block in an n-disk system is the maximum of n access delays. Using approximate ... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org