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Computers, IEEE Transactions on

Issue 7 • Date Jul 1991

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Displaying Results 1 - 12 of 12
  • Embedding complete binary trees into butterfly networks

    Page(s): 853 - 863
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    The authors present embeddings of complete binary trees into butterfly networks with or without wrap-around connections. Let m be an even integer and q=m+[log m]-1. The authors show how to embed a 2q+1-1-node complete binary tree T(q) into a (m+1)2m+1-node wrap-around butterfly Bw(m+1) with a dilation of 4, and how to embed T(q) into a (m+2)2m+2-node wrap-around butterfly Bw(m+2) with an optimal dilation of 2. They also present an embedding of a wrap-around butterfly Bw (m) into a (m+1)2m-node no-wrap-around butterfly B(m) with a dilation of 3. Using this embedding it is shown that T(q) can be embedded into a no-wrap butterfly B(m+1) [resp. B (m+2)] with a dilation of 8 (resp. 5) View full abstract»

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  • A modular fault-tolerant binary tree architecture with short links

    Page(s): 882 - 890
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone View full abstract»

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  • I/O overhead and parallel VLSI architectures for lattice computations

    Page(s): 843 - 852
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    The authors introduce input/output (I/O) overhead ψ as a complexity measure for VLSI implementations of two-dimensional lattice computations of the type arising in the simulation of physical systems. It is shown by pebbling arguments that ψ=Ω(n-1 ) when there are n2 processing elements available. If the results must be observed at every generation and if no on-chip storage is allowed, the lower bound is the constant 2. The authors then examine four VLSI architectures and show that one of them, the multigeneration sweep architecture also has I/O overhead proportional to n-1. A closed-form for the discrete minimization equation giving the optimal number of generations to compute for the multigeneration sweep architecture is proved View full abstract»

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  • The formal description and verification of hardware timing

    Page(s): 811 - 826
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    A formalism in which timing properties of digital hardware may be specified, derived, and formally verified is introduced as a rigorous theory for hardware timing. A rigorous modeling framework has been used to create a family of related verification techniques rather than a single timing analysis tool. This framework is based on a model of interacting finite state machines called CIRCAL, a formalism developed for the purpose of describing and validating complex concurrent systems. In this approach to hardware timing analysis, the presence of a composition operator is all-pervasive. It provides a single, uniform mechanism for describing the behavior of interacting hardware modules and for establishing and describing the timing properties of such modules View full abstract»

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  • Asynchronous disk interleaving: approximating access delays

    Page(s): 801 - 810
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    The performance implications of asynchronous disk interleaving are examined. In an asynchronous system, adjacent subblocks are placed independently of each other. Since each of the disks in such a system is treated independently while being accessed as a group, the access delay of a request for a data block in an n-disk system is the maximum of n access delays. Using approximate analysis, a simple expression for the expected value of such a maximum delay is obtained. The analysis approximation is verified by simulation using trace data; the relative error is found to be at most 6% View full abstract»

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  • Aliasing probabilities for feedback signature compression of test data

    Page(s): 867 - 873
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    A computationally efficient Markov state space model is developed for determining the aliasing probability of a linear feedback shift register when used for test data reduction. The model studied can be used to test data errors which have a constant of probability of error, correlated or repeated use errors, or time varying error probability. Based on a number of simulations of various error models and feedback polynomials it appears that a primitive polynomial, with about half its terms nonzero, has the best dynamic performance in most cases View full abstract»

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  • A VLSI modulo m multiplier

    Page(s): 873 - 878
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    A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROM-based structures is also provided. The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design. This structure can be used to implement a residue multiplier in arithmetic structures using residue number systems (RNSs). The complexity of this residue multiplier has been evaluated and lower complexity figures than for ROM-based multiply structures have been obtained under several hypotheses on RNS parameters View full abstract»

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  • A real-time locking protocol

    Page(s): 793 - 800
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    The authors examine a priority driven two-phase lock protocol called the read/write priority ceiling protocol. It is shown that this protocol leads to freedom from mutual deadlock. In addition, a high-priority transactions can be blocked by lower priority transactions for at most the duration of a single embedded transaction. These properties can be used by schedulability analysis to guarantee that a set of periodic transactions using this protocol can always meet its deadlines. Finally, the performance of this protocol is examined for randomly arriving transactions using simulation studies View full abstract»

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  • Load balancing in a hybrid ATPG environment

    Page(s): 878 - 882
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    The problem of balancing the computational load between fault simulation and conventional ATPG (automatic test program generation) is treated. A rule for switching from probabilistic to deterministic test pattern computation is derived. The criterion is based on a model of monitoring of the simulation process and on an online estimation of the fault detection probabilities. Using these probabilities and the operation characteristics of the ATPG program, one can decide whether it is more efficient to continue fault simulation or to proceed with algorithmic test pattern computation. A prototype of the hybrid ATPG system was implemented on an Apollo DN3000. Compared to a conventional ATPG system, better coverage and shorter generation times were obtained View full abstract»

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  • Performance analysis of multiple bus interconnection networks with hierarchical requesting model

    Page(s): 834 - 842
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    The authors study the performance of multiprocessor systems employing multiple buses as the interconnection networks under a nonuniform requesting model, called the hierarchical requesting model. The effective memory bandwidth is chosen as the performance measure. The networks investigated include multiple bus networks with full bus-memory connection, multiple bus networks with single bus-memory connection, and multiple bus networks with partial bus-memory connection. The authors also propose a type of multiple bus network with partial bus-memory connection, called partial bus networks with K classes. The N costs and fault-tolerant capabilities of the multiple bus networks are also evaluated and compared to one another. It is shown that the partial bus networks with K classes are useful in applications requiring high performance and degree of fault tolerance with moderate cost View full abstract»

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  • Parallel algorithms for image processing on OMC

    Page(s): 827 - 833
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    The author studies a class of VLSI organizations with optical interconnects for fast solutions to several image processing tasks. The organization and operation of these architectures are based on a generic model called OMC, which is used to understand the computational limits in using free space optics in VLSI parallel processing systems. The relationships between OMC and shared memory models are discussed. Also, three physical implementations of OMC are presented. Using OMC, several parallel algorithms for fine grain image computing are presented. A set of processor efficient optimal O(log N) algorithms and a set of constant time algorithms are presented for finding geometric properties of digitized images. Finally, designs tailored to meet both the computation and communication needs of problems such as those involving irregular sparse matrices are examined View full abstract»

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  • Translation of the problem of complete test set generation to pseudo-Boolean programming

    Page(s): 864 - 867
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    An attempt is made to demonstrate that the problem of complete test set generation is amenable to the problem of pseudo-Boolean programming. For this purpose, various types of faults, viz., single faults, multiple faults, and bridging faults, are considered. The key issue is to obtain logical expressions for the primary output line in terms of different faulty internal nodes to find real transforms. Using standard rules, the real transforms of a Boolean function can be obtained directly without any algebraic manipulation View full abstract»

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Albert Y. Zomaya
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albert.zomaya@sydney.edu.au