Issue 5 • Date May 2003
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Displaying Results 1 - 25 of 25
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Submicron InP-InGaAs single heterojunction bipolar transistors with f/sub T/ of 377 GHz
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PDF (253 KB)
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The origination and optimization of Si/SiO2 interface roughness and its effect on CMOS performance
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PDF (1583 KB)
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An integratable dual metal gate CMOS process using an ultrathin aluminum nitride buffer layer
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PDF (220 KB)
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A study of nitrogen peak location in gate oxides grown on nitrogen implanted substrates and its impact on boron penetration
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PDF (268 KB)
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Fabrication of SiC lateral super junction diodes with multiple stacking p- and n-layers
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PDF (261 KB)
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Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide
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PDF (212 KB)
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The statistical distribution of percolation current for soft breakdown in ultrathin gate oxide
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PDF (186 KB)
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Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics
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PDF (265 KB)
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Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions
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PDF (275 KB)
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A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage
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PDF (371 KB)
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Fully silicided NiSi gate on La2O3 MOSFETs
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PDF (246 KB)
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Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer
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PDF (247 KB)
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Reduction of carrier depletion in p/sup +/ polysilicon gates using laser thermal processing
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PDF (227 KB)
Aims & Scope
IEEE Electron Device Letters contains articles related to the theory, design, performance and reliability of electron devices.
Meet Our Editors
Editor-in-Chief
Yuan Taur
University of California at San Diego, ECE


