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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 6 • Date June 2003

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Displaying Results 1 - 9 of 9
  • Design of linear-phase variable 2-D digital filters using matrix-array decomposition

    Publication Year: 2003 , Page(s): 267 - 277
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (982 KB) |  | HTML iconHTML  

    A novel approach for designing linear-phase variable two-dimensional (2-D) digital filters is described, which is based on the matrix-array decomposition (MAD) of real-valued multidimensional arrays. By using the MAD, the desired variable 2-D magnitude response can be decomposed into the real-valued frequency response specifications of the normal zero-phase constant 2-D filters and the approximation specifications of multidimensional polynomials. Consequently, the problem of approximating the desired variable 2-D magnitude response can be decomposed into sub-problems that involve the design of zero-phase constant 2-D filters and the approximation of multidimensional polynomials. Once the zero-phase constant 2-D filters and the multidimensional polynomials are obtained, interconnecting them yields a zero-phase variable 2-D digital filter. Finally, a linear-phase variable 2-D digital filter can be easily obtained by simply modifying the zero-phase constant 2-D filters (noncausal) to linear-phase ones (causal) through shifting the filter coefficients. Since the sub-problems are much easier to solve than the direct approximation of the given variable 2-D magnitude specification, this MAD-based design approach is extremely efficient and straightforward. In designing zero-phase constant 2-D filters and approximating multidimensional polynomials, we also propose a new objective criterion for selecting appropriate filter orders and polynomial degrees. Furthermore, we also show that the resulting linear-phase variable 2-D filters have highly parallel structures and modularity, which are suitable for high-speed multidimensional signal processing. Two numerical examples are given to demonstrate the effectiveness of the MAD-based design approach. View full abstract»

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  • Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers

    Publication Year: 2003 , Page(s): 317 - 322
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    This paper presents an efficient implementation of digit-serial/parallel multipliers on 4-input look-up table (LUT)-based field programmable gate arrays (FPGAs). This subset of FPGA devices hide individual gate delays and add important wiring delay. These two facts produce important changes over the theoretical advantages of each topology. Architectural transformations are applied to obtain topologies with minimum logic depth and where the maximum clock speed is limited by the FPGA technology. The main results of applying those transformations to the different multipliers have been quantified for Altera FLEX10K family, and the conclusions have been extrapolated to other FPGA families. View full abstract»

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  • A width-recursive depth-first tree search approach for the design of discrete coefficient perfect reconstruction lattice filter bank

    Publication Year: 2003 , Page(s): 257 - 266
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (606 KB) |  | HTML iconHTML  

    The lattice structure two-channel orthogonal filter bank structurally guarantees the perfect reconstruction (PR) property. Thus, it is eminently suitable for hardware realization even under severe coefficient quantization condition. Nevertheless, its frequency response is still adversely affected by coefficient quantization. In this paper, a novel recursive-in-width depth-first tree search technique is presented for the design of lattice structure PR orthogonal filter banks subject to discrete coefficient value constraint. A frequency-response deterioration measure is developed to serve as a branching criterion. At any node, the coefficient which will cause the largest deterioration in the frequency response of the filter when quantized is selected for branching. The improvement in the frequency response ripple magnitude achieved by our algorithm over that by simple rounding of coefficient values differs widely from example to example ranging from a fraction of a decibel to over 10 dB. View full abstract»

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  • A CMOS fully balanced second-generation current conveyor

    Publication Year: 2003 , Page(s): 278 - 287
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (565 KB)  

    The design and implementation of a high performance CMOS fully balanced second-generation current conveyor (FBCCII) is presented. The proposed circuit is essential to extend the use of the CCII based circuits to integrated circuits (ICs) applications. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA). A low power class AB circuit realization is implemented in a 1.2-μm CMOS technology and its different characteristics are measured. Design examples of realizing fully balanced variable gain amplifiers (VGAs) and a bandpass filter based on the proposed FBCCII are given. Experimental results of the proposed circuits are included. View full abstract»

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  • An efficient pipelined FFT architecture

    Publication Year: 2003 , Page(s): 322 - 325
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    This paper presents an efficient VLSI architecture of the pipeline fast Fourier transform (FFT) processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By combining both the feedforward and feedback commutator schemes, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2. View full abstract»

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  • Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method

    Publication Year: 2003 , Page(s): 288 - 298
    Cited by:  Papers (24)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (902 KB) |  | HTML iconHTML  

    This paper describes a new method for extracting both instantaneous and rms sinusoidal jitter from phase-locked loops (PLL) output signals. The method is based on analytic signal theory and utilizes the Hilbert transform to extract phase information from a PLL signal. Both the theoretical basis and fundamental concepts of the new method are explained. A unified review of conventional methods is also presented. Results of Matlab simulations validate the performance of the new method for measuring jitter, and it is further validated by comparing experimental sinusoidal jitter results with those of a time interval analyzer. View full abstract»

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  • On the exact realization of log-domain elliptic filters using the signal flow graph approach

    Publication Year: 2003 , Page(s): 325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (142 KB) |  | HTML iconHTML  

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  • A novel low-voltage switched-capacitor input branch

    Publication Year: 2003 , Page(s): 315 - 317
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    A novel switched-capacitor (SC) input branch is proposed for low-voltage applications. This circuit can be used at the very first input providing external signals. It not only eliminates the problem of a floating switch from the signal path, but also reduces circuit complexities of earlier low-voltage input branches. This is achieved by modifying the common SC branch. In the proposed configuration, there is no need for a boosted-clock voltage, a switched-opamp method, or a reset-opamp technique. View full abstract»

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  • Behavioral modeling for analog system-level simulation by wavelet collocation method

    Publication Year: 2003 , Page(s): 299 - 314
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (878 KB) |  | HTML iconHTML  

    In this paper, we propose a wavelet collocation method with nonlinear companding to generate behavioral models for analog circuits at the system level. During the overall process of circuit modeling, nonlinear function approximation is an important issue to accurately capture the nonideal input-output relations of analog circuit blocks. While a great number of previous research works focus on the high-dimensional top-down design/synthesis model, which involves large analog design spaces, this paper primarily concentrates on the bottom-up verification model requiring both simple representation and high accuracy. Taking advantage of the local support of wavelet bases, a nonlinear companding method is developed to control the modeling error distribution based on system-level simulation requirements. It, in turn, significantly improves the simulation efficiency at the system level. To demonstrate the promising features of the proposed method, two circuit examples, a fourth-order switched-current filter and a voltage-controlled oscillator, are employed to build the behavioral models. View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope