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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 1 • Date Jan. 2003

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Displaying Results 1 - 11 of 11
  • Abstracts

    Page(s): 2 - 4
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    Freely Available from IEEE
  • Control-based life-cycle forecasting

    Page(s): 5 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (711 KB)  

    In this paper, the authors lay out a process for effective monitoring and control of a life cycle forecast. This algorithm and forecasting technique is based on the idea that a forecast should not be changed unless it is shown to be an invalid forecast using standard statistical means. The approach is a control-based approach that serves to greatly reduce the amount of forecasting that must be performed and it does not harm the accuracy of the overall forecast. This work builds on earlier work by Foote (see IIE Trans., vol.27, p. 210-216, 1995) in the area of aircraft spare parts. At Compaq Computer Corporation, the amount of forecasting was cut by over 50% where this algorithm was implemented. View full abstract»

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  • Optimizing the operation sequence of a chip placement machine using TSP model

    Page(s): 14 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB) |  | HTML iconHTML  

    Surface mount component placement machines are being widely used in electronic manufacturing industry for automated placement of components on printed wire boards (PWBs). Their performance is determined by their board assembly time. Factors that determine this include the machine's architecture and placement sequence algorithm, and component locations on the board. For a given machine and a board, the assembly time can be improved by optimizing the placement sequence algorithm. This paper presents a formulation and solution of the assembly time optimization problem for the FUJI FCP-IV component placement machine. The formulation gives a mathematical description of the assembly time that can be optimized as an integer programming problem. A near-optimal solution that can be obtained in a computationally efficient manner has been obtained by relaxing the problem to an instance of the traveling salesman problem (TSP). Simulation has been conducted on some actual boards and the results have been compared with those obtained by the actual runs at Lexmark, Inc., Lexington, KY. This shows that significant reduction in component placement time can be achieved by the proposed optimization algorithm. View full abstract»

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  • Evaluation and optimization of package processing and design through solder joint profile prediction

    Page(s): 68 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1865 KB) |  | HTML iconHTML  

    Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design. View full abstract»

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  • An approach for grouping circuit cards into families to minimize assembly time on a placement machine

    Page(s): 22 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    This paper addresses a difficult problem that often arises in printed circuit card assembly systems: how should circuit cards be grouped into families to decrease total assembly time? Traditional approaches to this problem focus on setup time, without considering the possible impacts on processing time. A new approach for selecting card families to be processed on an assembly machine is developed to minimize total assembly time through the joint consideration of setup time and processing time. The overall approach for addressing the card grouping problem involves capturing the lower level machine configuration decisions through an empirical estimator function and incorporating this function with the higher level card grouping problem. The card grouping problem is solved using a branch-and-bound algorithm supplemented by techniques to improve the solution time. An industrial case study is conducted for a turret style placement machine, a Panasonic MV150 machine. The results demonstrate the positive impact of including the lower level decisions on the total assembly time and system throughput for certain types of assembly machines. In addition, this research provides insight on other process planning problems, such as line assignment and card sequencing, by demonstrating the importance of incorporating the related lower level decision problems. View full abstract»

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  • Finite element contact analysis on a horn-holder assembly for wire bonding

    Page(s): 46 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2330 KB) |  | HTML iconHTML  

    The joint structure of a transducer horn-holder assembly for a wire bonder was examined through finite element contact analysis. Three-dimensional modeling and analysis was carried out to survey the internal physics of this structure and to verify the accuracy of a proposed computation relative to measurement. After validation, a two-dimensional model was built to conduct parametric studies and improve the efficiency and speed of the computation. Several factors such as boundary conditions, modeling boundary, and mesh density, were considered to obtain consistency with the three-dimensional analysis. Arc angle and the position of each holder boss were chosen as design parameters. A designed computation approach was applied for efficiency in computation. As a result, a guideline for holder boss design was suggested, and the main factors and their influence on stress concentration in the transducer horn were surveyed. View full abstract»

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  • New techniques for the design of advanced ultrasonic transducers for wire bonding

    Page(s): 37 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1078 KB) |  | HTML iconHTML  

    A new high-frequency ultrasonic transducer, in particular for the application wire-bonding, has been conceived, designed, prototyped, and tested. In the design phase an advanced approach was used and established. The method is based on the two basic principles of modularity and iteration. The transducer is decomposed in its elementary components. For each component an initial draft is obtained with finite-elements-method simulations (FEM). The simulated ultrasonic modules are then built and characterized experimentally through laser-interferometry measurements and electrical resonance spectra. The comparison of simulation results with experimental data allows the parameters of FEM models to be iteratively adjusted and optimized. The achieved FEM simulations exhibit a remarkably high predictive potential and allow full control on the vibration behavior of the ultrasonic modules and of the whole transducer. The new transducer is fixed on the welding device with a flange whose special geometry was calculated by means of FEM simulations. This flange allows the converter to be attached on the welding device not only in longitudinal nodes but also in radial nodes of the ultrasonic field excited in the horn. This leads to a total decoupling of the transducer to the welding device, which has so far been unheard of. The new approach to mount ultrasonic transducers on a welding-device is of major importance not only for wire-bonding but also for all high-power ultrasound applications. View full abstract»

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  • Modeling and characterization of the polymer stud grid array (PSGA) package: electrical, thermal and thermo-mechanical qualification

    Page(s): 54 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2705 KB) |  | HTML iconHTML  

    We characterize the polymer stud grid array (PSGA) package electrically, thermally and thermo-mechanically for successful commercial application. For the electrical characterization, we extract lumped parameter resistance-inductance-capacitance (RLC) models for the interconnects from simulations. We also measure the RF performance of the package on printed circuit board (PCB) test structures. The average self-inductance from the wirebond pad to the bottom of the stud is 0.53 nH and the total capacitance to the ground is 0.26 pF for an interconnection of the periphery of the over the edge (OTE) type PSGA. The lumped RLC model is verified by full three-dimensional (3-D) EM simulations. Simulation models also indicate that the "Micro-via" (μ-via) type of interconnection on the PSGA package improves performance by decreasing the inductance on an average by 60%. Thermal characterization involves the development of a steady-state thermal compact model with six nodes for the 72-pin PSGA. We also perform transient thermal measurements on test packages to fine-tune the detailed model. For the thermo-mechanical case we test the first level and second level reliability by experiments and optimize them using simulations. The board level reliability for the 72-pin PSGA mounted on a PCB is very high (N50%>10000 cycles). Simulations also show a higher reliability for the PSGA than the plastic ball grid array (PBGA). View full abstract»

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  • A fuzzy system for package shipment selection for electronic systems

    Page(s): 31 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (910 KB)  

    The last stage of any type of manufacturing industry, is the packaging for shipment. Manufactured items can come in multiple sizes, weights, and sensitivity to shipment hazards. Yet, the number of standard packaging methods, such as cardboard box sizes or plastic-wrapping bags is limited. Thus, before the shipping of any type of products to their final destination, suitable packages have to be selected. Failure to select the best package for the shipment, may induce additional shipment costs or the possibility of shipping damage. Motorola Arad is the manufacturer of a large variety of electronic systems for Motorola, Inc. It has to handle many types of shipment orders each week. A prototype expert system was implemented, which uses fuzzy rules and fuzzy variables to recommend the best packaging method for each item and each shipment. Utilizing the fuzzy expert system resulted in significant decrease in the packaging volumes and packaging costs. View full abstract»

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  • Processing of fluxing underfills for flip chip-on-laminate assembly

    Page(s): 75 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1142 KB) |  | HTML iconHTML  

    Fluxing underfill eliminates process steps in the assembly of flip chip-on-laminate (FCOL) when compared to conventional capillary flow underfill processing. In the fluxing underfill process, the underfill is dispensed onto the board prior to die placement. During placement, the underfill flows in a "squeeze flow" process until the solder balls contact the pads on the board. The material properties, the dispense pattern and resulting shape, solder mask design pattern, placement force, placement speed, and hold time all impact the placement process and the potential for void formation. A design of experiments was used to optimize the placement process to minimize placement-induced voids. The major factor identified was board design, followed by placement acceleration. During the reflow cycle, the fluxing underfill provides the fluxing action required for good wetting and then cures by the end of the reflow cycle. With small, homogeneous circuit boards it is relatively easy to develop a reflow profile to achieve good solder wetting. However, with complex SMT assemblies involving components with significant thermal mass this is more challenging. View full abstract»

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  • Phase equilibria and thermodynamic properties of Sn-Ag based Pb-free solder alloys

    Page(s): 84 - 89
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (474 KB) |  | HTML iconHTML  

    We have recently developed a thermodynamic database for micro-soldering alloys, alloy database for micro-solders (ADAMIS). ADAMIS which consists of the elements Ag, Bi, Cu, In, Pb, Sb, Sn, and Zn has been constructed by the calculation of phase diagrams (CALPHAD) method. The thermodynamic parameters for describing the Gibbs energy of the liquid and solid phases have been evaluated by optimizing the experimental data on phase boundaries and thermo-chemical properties. In this paper, the phase equilibria and the related thermodynamic properties pertaining to the Sn-Ag-X (X=Bi, In, Cu, and Zn) alloys are examined using ADAMIS. Typical examples of the isothermal and vertical section phase diagrams, liquidus surface, etc. for these promising lead-free solders are presented. In addition, ADAMIS is also applied to calculate the nonequilibrium solidification process using the Scheil model. View full abstract»

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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University