By Topic

Advanced Packaging, IEEE Transactions on

Issue 1 • Date Feb. 2003

Filter Results

Displaying Results 1 - 13 of 13
  • Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

    Page(s): 90 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of wirebonding techniques for contacting high concentrator solar cells

    Page(s): 47 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (357 KB)  

    The results of the wirebonding technique application to make connections on high concentrator solar cells are presented in this paper. The most usual wirebonding techniques in current microelectronic industry have been analyzed (i.e., aluminum wedge bonding and thermosonic gold ball bonding). In the first part of the paper the influence of wirebonding processes on solar cell performance is discussed theoretically. The theoretical approach is followed by a comprehensive experimental analysis, which focuses on: a) the influence of mechanical damage on the device I-V curve; b) bondability analysis; c) the influence of wirebonding damage on device lifetime; d) analysis of the electrical resistance of the connection. Finally some conclusions of practical interest are drawn and the main results of the work are summarized. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Polymer-ceramic nanocomposite capacitors for system-on-package (SOP) applications

    Page(s): 10 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (966 KB)  

    This work focuses on optimizing the dispersion of nanosized ceramic particles for achieving higher dielectric constant, thereby higher capacitance density in polymer/ceramic nanocomposites. It has been observed that high solids loading leads to entrapment of porosity in the microstructure which lowers the effective dielectric constant of the films. The amount of solvent in the suspension and the speed at which spin coating was performed were found to impact the dielectric constant of high filler content nanocomposites. The interplay between the rheological properties of the suspension and processing parameters such as solvent content and coating speeds and its impact on the dielectric properties of the film are discussed. Porosity of thin film composites was measured for the first time to study the impact of these processing parameters. Powders of different particle sizes were mixed to obtain bimodal particle size distribution in order to increase the packing density of the composite. Packing density was improved by modifying the dispersion methodology. A nanocomposite with dielectric constant as high as 135 was obtained for the first time in the low-cost printed wiring board compatible epoxy system. A capacitance densities of ∼35 nF/cm2 on a nominal 3.5 micrometer films was achieved on PWB substrates with high yield. The manufacturability of these formulated nanocomposites and their applications as decoupling capacitors have been tested using a large area (300 mm × 300 mm) system-on-package (SOP) chip-to-chip communication test vehicle. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Elastomer chip sockets for reduced thermal mismatch problems and effortless chip replacement, preliminary investigations

    Page(s): 33 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1687 KB) |  | HTML iconHTML  

    To avoid the problem with thermo-mechanical stress induced fatigue using conventional flip-chip mounting of bare chips, an elastic chip socket has been developed. The socket is made by casting silicone elastomer into micro structured silicon molds to form micro bump arrays. After the elastomer is cured and released from the mold, a metal layer is deposited and patterned. A chip is placed in the socket utilizing guiding structures for chip self alignment. The chip is then held in place by a spring loaded back-plate which can also serve as a heat sink for highly effective chip cooling. Since no adhesives, underfills or solders are used, the rework process becomes very simple and it can also be repeated many times for the same socket. Initial contact resistance and thermo-mechanical robustness measurements indicates that this type of sockets could work as a superior replacement for conventional flip-chip technologies in many applications. The particular design of the contact bumps results in metal structures that resemble (although up side down) and are scalable as those in the Chip-First technology. Preliminary thermal shock experiments from room temperature to liquid nitrogen and back show good survival. Thus, this new chip interconnect method indicates the possibility of getting the advantages of the Chip-First technology while eliminating the demand of placing the chip first. The concept will work for chips with rim positioned pads as well as for high density area arrays. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Technology for very dense hybrid detector arrays using electroplated indium solderbumps

    Page(s): 60 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB) |  | HTML iconHTML  

    This paper presents a detailed overview of the process steps involved in the hybrid integration process of III-V infrared detector arrays and silicon readout electronics. This process is divided in distinct parts: the postprocessing of the Silicon readout circuit, the Indium solderbump formation by electroplating and the flip-chip process. In contrast to commercially available hybrid arrays, the indium solderbump technology is applied to the III-V array only and not to the silicon readout. This causes specific requirements to the III-V metallization sequence prior to electroplating in order to obtain proper reflow. Two different silicon postprocessing schemes are described. Arrays of 128×128, 256×256 and 320×256 In(Ga)As and InAsSb photovoltaic infrared detectors have been integrated with dedicated in-house and commercial readout using this process. The feasibility of achieving 10 μm hybrid integration pitch is also shown. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Microwave circuits in multilayer inorganic-organic polymer thin film technology on laminate substrates

    Page(s): 81 - 89
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    Requirements of higher performance, reduced size, weight and cost of high-frequency (HF) devices has led to the search for new: materials, material combinations, methods, processes and production equipment. Efficient technologies for producing HF-circuits and integral passives are looked for. Also of interest are integrated packaging solutions for high frequency electrical packaging and optical interconnects and packaging. Sequentially build up multi-layers have been deposited on a low cost FR-4 epoxy substrate. The dielectric layers consist of a photo-patternable inorganic-organic hybrid polymer (ORMOCER) and the metallization is Cu. An UV-exposure equipment enabling projection patterning with 5 μm resolution have been used. The produced microstrip lines, ring resonators, vias, stacked capacitors and filters have been characterized at frequencies from 1 to 40 GHz showing the potential of the new dielectric materials and processing technologies for microwave applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interface delamination in plastic IC packages induced by thermal loading and vapor pressure - a micromechanics model

    Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (549 KB)  

    A micromechanics model and an associated computational scheme are proposed to study interface delamination in plastic integrated circuit (IC) packages induced by thermal loading and vapor pressure. The die and die-pad are taken as elastic materials, while the die-attach and molding compound are taken as elasto-visco-plastic materials. The interface between molding compound and the die-pad is characterized by a cohesive law. The key parameters of this law are the interface strength and interface energy. The vapor-induced pressure along the interface is incorporated by way of a micromechanics model. Parametric studies are conducted to understand interface properties and vapor pressure effects on interface delamination. Under purely thermal loading, both weak and strong interfaces are highly resistant to interface failure. However, the combined effects of thermal loading and vapor pressure arising from moisture trapped within the interface can cause total delamination at the interface. Once delamination has initiated at a weak interface, no significant increase in thermal loading and vapor pressure is required for the delaminated zone to grow to a macro-crack and subsequently to catastrophic failure referred to as popcorn cracking. The critical factors controlling the occurrence of popcorn cracking are the interface adhesion strength and interface vapor pressure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An improvement of thermal conductivity of underfill materials for flip-chip packages

    Page(s): 25 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1102 KB) |  | HTML iconHTML  

    Effective heat dissipation is crucial to enhance the performance and reliability of electronic devices. In this work, the performance of encapsulants filled with carbon fiber was studied and compared with silica filled encapsulants. Encapsulants filled with mixed combination of fillers for optimizing key properties were also investigated. The thermal and electrical conductivities were investigated and glass transition temperature (Tg), thermal expansion coefficient (TCE), and storage modulus (E') of these materials were studied with thermal analysis methods. The composites filled with both carbon fiber and silica showed an increase of thermal conductivity three to five times of that of silica filled encapsulants of the same filler loading while maintaining/enhancing major mechanical and thermal properties. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Flip-chip on flex integrated power electronics modules for high-density power integration

    Page(s): 54 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1003 KB)  

    Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application of the cavity model to lossy power-return plane structures in printed circuit boards

    Page(s): 73 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (734 KB) |  | HTML iconHTML  

    Power-return plane pairs in printed circuit boards are often modeled as resonant cavities. Cavity models can be used to calculate transfer impedance parameters used to predict levels of power bus noise. Techniques for applying the cavity model to lossy printed circuit board geometries rely on a low-loss assumption in their derivations. Boards that have been designed to damp power bus resonances (e.g., boards with embedded capacitance) generally violate this low-loss assumption. This paper investigates the validity of the cavity model when applied to printed circuit board structures where the board resonances are significantly damped. Cavity modeling results for sample lossy power-return plane structures are validated using a three-dimensional full wave numerical code. A simple method is also established to check the validity of the cavity model for a power-return plane structure with imperfect conductors and lossy dielectric substrates. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dielectric nanocomposites for integral thin film capacitors: materials design, fabrication and integration issues

    Page(s): 17 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (654 KB)  

    Nanocomposites of organically modified barium titanate (BTO) nanoparticles in an epoxy matrix have been synthesized and evaluated as dielectrics for the fabrication of integral thin film capacitor arrays. Organic modification of the polymer inorganic interface has been used as a design tool to control the cross link density of the polymeric matrix and the interfacial interactions. Impedance spectra generated with model networks has been employed to analyze the experimental data and to model the role of the ceramic core, interface and the polymer matrix in determining the dielectric behavior of the nanocomposites. Stealth decoupling capacitor arrays were fabricated employing BTO-Epoxy nanocomposite thin films as dielectric layer. Capacitor arrays were fabricated by patterning the top electrode in the glass/Al/BTO-epoxy/Al heterostructures employing a photolithographic process and their electrical performance characterized. The role of an organically modified interface in limiting the thermal diffusion of copper metal in the composite thin film has been investigated employing Rutherford backscattering spectroscopy. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Finite element analysis of post-weld shift during fiber pigtail of 980 nm pump lasers

    Page(s): 41 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (647 KB) |  | HTML iconHTML  

    Post-weld-shift (PWS) during pigtailing of telecommunication laser diodes, such as pump lasers, has been numerically modeled and studied experimentally. The results demonstrate that the PWS can be minimized by properly controlling the laser beam energy delivery. A 3-D finite element model has been developed for effectively predicting the PWS. The results were implemented into the alignment algorithm achieving superior performance figures. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast analysis of bounces on power/ground planes using even-odd partition

    Page(s): 65 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    A novel method for analyzing the bounces on structure of parallel power/ground planes by using the even-odd mode partition is presented in this paper. Based on the distributed RLCG circuit model derived from the two dimensional electromagnetic field equations of the power/ground planar structure, this method can speed up the circuit simulation of the bounces on power/ground planes by using even-odd mode partition. Furthermore, the method can be used to evaluate the effects of the terminated decoupling capacitors and the hole structures on power/ground plane. The numerical examples demonstrate that the method has both high efficiency and good precision. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering