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Computers, IEEE Transactions on

Issue 5 • Date May 2003

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Displaying Results 1 - 16 of 16
  • A quantification of aborting effect for real-time data accesses

    Page(s): 670 - 675
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB) |  | HTML iconHTML  

    This paper proposes a generic framework to integrate real-time scheduling algorithms, conventional concurrency control algorithms, and aborting algorithms. The schedulability of a transaction system is improved by aborting excessive blocking from lower priority transactions. A schedulability analysis model is proposed to better manage the schedulability of a transaction system. View full abstract»

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  • Transmission time analysis for the parallel asynchronous communication scheme

    Page(s): 558 - 571
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3391 KB) |  | HTML iconHTML  

    In asynchronous systems, the sender encodes a data word with a code word from an unordered code and transmits the code word on the parallel bus lines. In this paper, a transmission time analysis for the above parallel asynchronous communication scheme is presented. It is proven that the average transmission time for a code word is a strictly increasing function of the weight of the code word and it approaches the worst transmission time possible when the weight goes to infinity. This implies that fast parallel asynchronous systems can be designed using low weight codes. This paper also analyzes the transmission time performances of the proximity detecting codes and gives some efficient low constant weight code designs. View full abstract»

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  • Schedulability and performance analysis of the similarity stack protocol

    Page(s): 658 - 669
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (837 KB) |  | HTML iconHTML  

    We propose a class of real-time data access protocols called SSP (similarity stack protocol). The correctness of SSP schedules is justified by the concept of similarity which allows different but sufficiently timely data to be used in a computation without adversely affecting the outcome. SSP schedules are deadlock-free, subject to limited blocking, and do not use locks. We give a schedulability bound for SSP and also report simulation results which show that SSP is especially useful for scheduling real-time data access on multiprocessor systems. Finally, we present a variation of SSP which can be implemented in an autonomous fashion in the sense that scheduling decisions can be made with local information only. View full abstract»

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  • Thinning schemes for call admission control in wireless networks

    Page(s): 685 - 687
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB)  

    In this paper, we present new call admission control schemes, thinning schemes, which smoothly reduce traffic admission rates. Performance analysis is carried out and new analytical results are obtained. It demonstrates that thinning schemes can be used to derive many known call admission control schemes. View full abstract»

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  • A counterexample to Tang and Padubidri's claim about the bisection width of a diagonal mesh

    Page(s): 676 - 677
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    A counterexample is presented to disprove Tang and Padubidri's (1994) claim about the bisection width of a diagonal mesh. View full abstract»

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  • User-level QoS-adaptive resource management in server end-systems

    Page(s): 678 - 685
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1135 KB) |  | HTML iconHTML  

    Proliferation of QoS-sensitive client-server Internet applications such as high-quality audio, video-on-demand, e-commerce, and commercial Web hosting has generated an impetus to provide performance guarantees. These applications require a guaranteed minimum amount of resources to operate acceptably to the users, thus calling for QoS-provisioning mechanisms. One good place to locate such mechanisms is in server communication subsystems. Server-side communication subsystems manage an increasing number of connection end-points, thus readily controlling important bottleneck resources. We propose, implement, and evaluate a novel communication server architecture that maximizes the aggregate utility of QoS-sensitive connections for a community of clients even in the case of overload. A contribution of this architecture is that it manages QoS from the user space and is transparent to the application. It does not require modifications to the OS kernel, which improves portability and reduces development cost. Results from an experimental evaluation on a microkernel indicate that it achieves end-system overload protection and traffic prioritization, improves insulation between independent clients, adapts to offered load, and enhances aggregate service utility. View full abstract»

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  • Adaptive approaches to relieving broadcast storms in a wireless multihop mobile ad hoc network

    Page(s): 545 - 557
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3107 KB) |  | HTML iconHTML  

    In a multihop mobile ad hoc network, broadcasting is an elementary operation to support many applications. Previously, it is shown that naively broadcasting by flooding may cause serious redundancy, contention, and collision in the network, which we refer to as the broadcast storm problem. Several threshold-based schemes are shown to perform better than flooding in that work. However, how to choose thresholds also poses a dilemma between reachability and efficiency under different host densities. In this paper, we propose several adaptive schemes, which can dynamically adjust thresholds based on local connectivity information. Simulation results show that these adaptive schemes can offer better reachability as well as efficiency as compared to the previous results. View full abstract»

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  • Disproving the perfect-rate property of data-flow graphs unfolded by the least common multiple of the number of loop register

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (205 KB) |  | HTML iconHTML  

    In their 1991 paper "Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding", Parhi and Messerschmidt stated a perfect-rate property on unfolded data-flow graphs (DFGs). This is disproven by a simple counter example. View full abstract»

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  • Isomorphic strategy for processor allocation in k-ary n-cube systems

    Page(s): 645 - 657
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4659 KB) |  | HTML iconHTML  

    Due to its topological generality and flexibility, the k-ary n-cube architecture has been actively researched for various applications. However, the processor allocation problem has not been adequately addressed for the k-ary n-cube architecture, even though it has been studied extensively for hypercubes and meshes. The earlier k-ary n-cube allocation schemes based on conventional slice partitioning suffer from internal fragmentation of processors. In contrast, algorithms based on job-based partitioning alleviate the fragmentation problem but require higher time complexity. This paper proposes a new allocation scheme based on isomorphic partitioning, where the processor space is partitioned into higher dimensional isomorphic subcubes. The proposed scheme minimizes the fragmentation problem and is general in the sense that any size request can be supported and the host architecture need not be isomorphic. Extensive simulation study reveals that the proposed scheme significantly outperforms earlier schemes in terms of mean response time for practical size k-ary and n-cube architectures. The simulation results also show that reduction of external fragmentation is more substantial than internal fragmentation with the proposed scheme. View full abstract»

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  • Tests and tolerances for high-performance software-implemehted fault detection

    Page(s): 579 - 591
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (541 KB) |  | HTML iconHTML  

    We describe and test a software approach to fault detection in common numerical algorithms. Such result checking or algorithm-based fault tolerance (ABFT) methods may be used, for example, to overcome single-event upsets in computational hardware or to detect errors in complex, high-efficiency implementations of the algorithms. Following earlier work, we use checksum methods to validate results returned by a numerical subroutine operating subject to unpredictable errors in data. We consider common matrix and Fourier algorithms which return results satisfying a necessary condition having a linear form; the checksum tests compliance with this condition. We discuss the theory and practice of setting numerical tolerances to separate errors caused by a fault from those inherent in finite-precision floating-point calculations. We concentrate on comprehensively defining and evaluating tests having various accuracy/computational burden tradeoffs, and we emphasize average-case algorithm behavior rather than using worst-case upper, bounds on error. View full abstract»

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  • An intelligent cache system with hardware prefetching for high performance

    Page(s): 607 - 616
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3099 KB) |  | HTML iconHTML  

    We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. The proposed cache, which we call a selective-mode intelligent (SMI) cache, consists of three parts: a direct-mapped cache with a small block size, a fully associative spatial buffer with a large block size, and a hardware prefetching unit. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer for a time period. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. The overhead of this prefetching operation is shown to be negligible. We also show that the prefetch operation is highly accurate: Over 90 percent of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance. Also, the SMI cache can reduce the miss ratio by around 20 percent and the average memory access time by 10 percent, compared with a victim-buffer cache configuration. View full abstract»

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  • Computing packet loss probabilities in multiplexer models using rational approximation

    Page(s): 633 - 644
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (977 KB) |  | HTML iconHTML  

    A statistical multiplexer is a basic model used in the design and the dimensioning of communication networks. The multiplexer model consists of a single server queue with constant service time and a more or less complicated arrival process. The aim is to determine the packet loss probability as a function of the capacity of the buffer. In this paper, we show how rational approximation techniques may be applied to compute the packet loss efficiently. The approach is based on the knowledge of a limited number of sample values, together with the decay rate of the probability distribution function. A strategy is proposed where the sample points are chosen automatically. The accuracy of the approach is validated by comparison with both analytical results obtained using a matrix-analytic method and simulation results. View full abstract»

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  • New CRT-based RNS converter using restricted moduli set

    Page(s): 572 - 578
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1721 KB) |  | HTML iconHTML  

    This paper presents a new RNS converter using any number of relatively prime moduli of the form 2n and 2n ± 1. With the exception of common 3 moduli sets such as {2n - 1,2n, 2n + 1}, FINS output converters based on the CRT require the computation of a sum of products modulo a large number. The new converter presented in this paper uses the fractional representation for the output and eliminates the requirement for multiplications, thereby reducing area and delay. Further area improvements are possible by exploiting the period of terms to be added. An algorithmic approach is used to obtain full adder-based architectures that are optimized for area and delay. View full abstract»

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  • Reduction of sizes of decision diagrams by autocorrelation functions

    Page(s): 592 - 606
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    This paper discusses optimization of decisions diagrams (DDs) by total autocorrelation functions. We present an efficient algorithm for construction of linearly transformed binary decision diagrams (LT-BDDs) and Linearly transformed multiterminal BDDs (LT-MTBDDs) for systems of Boolean functions, based on linearization of these functions by the corresponding autocorrelation functions. Then, we present a method for reduction of sizes of DDs by a level-by-level reduction of the width of DDs using the total autocorrelation functions. The approach provides for a simple procedure for minimization of LT-BDDs and LT-MTBDDs and upper bounds on their sizes. Experimental results for benchmarks illustrate that the proposed method on average is very efficient. View full abstract»

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  • Switch MSHR: a technique to reduce remote read memory access time in CC-NUMA multiprocessors

    Page(s): 617 - 632
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5708 KB) |  | HTML iconHTML  

    A remote memory access poses a severe problem for the design of CC-NUMA multiprocessors because it takes an order of magnitude longer than the local memory access. The large latency arises partly due to the increased distance between the processor and remote memory over the interconnection network. In this paper, we develop a new switch architecture, called Switch MSHR (SMSHR), which provides the cache block to the requesting processors without those requests having to go to the home memory. The SMSHR idea is based on providing a few miss status holding registers (MSHRs) in each switch that keep track of read requests to the memory. The SMSHR blocks secondary requests to the same memory block and provides them with a copy of the block when the primary reply returns. The SMSHR design is then extended to include a switch cache, which can temporarily save a copy of the data block for later use. We provide basic block designs for the SMSHR and SIVISHR+cache architectures in this paper. We explore the design space by modeling the new switch architectures in a detailed execution-driven simulator and analyze the performance benefits. Our Simulation results show that applications with a high degree of data sharing benefit tremendously from the SMSHR and SMSHR+cache techniques. View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org