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Design & Test of Computers, IEEE

Issue 2 • Date June 1991

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Displaying Results 1 - 7 of 7
  • Computer-aided prototyping for ASIC-based systems

    Page(s): 4 - 10
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    The use of computer-aided prototyping (CAP) with the RPM Emulation System is described. RPM creates a hardware functional prototype from an ASIC or full-custom chip netlist. It reads the chip netlist and then converts the chip design gates into a prototype design. It then synthesizes the prototype design, obtaining the information it needs to configure the reprogrammable hardware, primarily with partitioning and placement and routing technology. Finally, it physically implements the prototype design by electronically configuring the reprogrammable hardware. RPM includes embedded tools for interactive debugging with access to any internal design node, and a facility for handling quick incremental changes to the design. It is argued that other techniques such as silicon prototyping and manual prototyping are not practical; silicon has a poor debugging ability, and manual prototyping cannot handle large designs. The practical benefits of CAP are discussed.<> View full abstract»

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  • A rapid-prototyping environment for digital-signal processors

    Page(s): 11 - 25
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    A description is given of the Diodes system, a complete rapid prototyping, debugging, and test environment including both hardware and software, for the design of digital-signal-processing chips. The test circuitry in Diodes differs from that in many systems, including those based on boundary scan, by offering full-speed circuit testing and the observation of internal nodes during real time. Diodes also achieves nearly 100% fault coverage because chips are composed of numerous chunks, each of which is tested exhaustively. The discussion covers the high-density interconnection technology and the concepts on which Diodes is based, two types of chips that have been designed, fabricated, and tested for Diodes: module assembly and fabrication; synthesis software; on-chip testing; Diodes test circuitry; test modes; and hardware and software debugging. Diodes is compared with other testing approaches and other rapid prototyping systems.<> View full abstract»

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  • Rapid prototyping of high-speed communications chips

    Page(s): 27 - 39
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    A description is given of the Mulga symbolic design system, which is based on the virtual-grid concept, a structural approach to symbolic design that extends naturally to a hierarchical design. The relative placement of the circuit elements is determined by their location on the input grid. This grid serves only to delineate the relative topology of the circuit elements and does not correspond to a physical coordinate system. Experience with Mulga for more than seven years is reported, showing that it has been very effective in providing quality layout and high productivity, enabling small teams to do entire designs, from algorithms to logic design to layout. A new symbolic design system called Dasl is also reported. The advantages of using symbolic layout for generator systems and silicon compilers are discussed.<> View full abstract»

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  • Fast prototyping of datapath-intensive architectures

    Page(s): 40 - 51
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    A description is given of Hyper, a synthesis environment for real-time systems with datapath-intensive architectures. Hyper uses a single, global quality measure throughout the system to drive the exploration of the design space. This approach effectively merges the allocation of hardware, the application of transformations, and the handling of hierarchy in a consistent way. Hyper's modular organization around a central database also allows new software modules to be introduced easily. The discussion covers behavioral specification, module selection, exploring the design space, transformations, scheduling and assignment, and hardware mapping. Four versions of an IIR filter generated using Hyper and Lager IV are compared. It is seen that layouts generated using Hyper are more area efficient than layouts done using the more traditional methods based on one-to-one mapping or the use of multiprocessors.<> View full abstract»

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  • Rapid prototyping for DSP systems with multiprocessors

    Page(s): 52 - 62
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    The authors describe the hardware and software of a system for prototyping digital-signal-processing applications by using commercially available digital-signal processors linked to form multiprocessors. The graphical programming environment makes it easier to program, compile, debug, and test DSP algorithms. The system reduces the cost of application prototyping, making it a feasible step at early design stages. To demonstrate the advantages of their approach, the authors explain how they prototyped a digital audio broadcast system. The complexities encountered highlight the limitations of the system.<> View full abstract»

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  • Testing interconnections to static RAMs

    Page(s): 63 - 71
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    A method for testing the interconnections of ordinary static RAMs with a processor that has a boundary-scan register and an IEEE 1149.1 test-access port is described. The method uses an enhanced boundary-scan-register design that manipulates the test-access-port controller states to meet the static RAM's timing constraints. The implementation is more economical than a boundary-scan register that strictly conforms to IEEE 1149.1. Test operation is more efficient, requiring a third of the number of scan operations. A test-pattern set and a method for detecting and diagnosing the interconnection faults on RAMs are also described. The test-pattern set can be enhanced as necessary to increase coverage and diagnosing ability and to handle any RAM configuration. The implementation of the proposed boundary-scan register is independent of the test algorithm used. It is believed that the methodology is extendable to RAMs that use an access protocol different from the one described, for example dynamic RAMs and synchronous RAMs.<> View full abstract»

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  • A test-pattern-generation algorithm for sequential circuits

    Page(s): 72 - 85
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    A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called Essential, takes advantage of a procedure for learning global implications. It uses static and dynamic dominance relationships among signals, the concept of the potential propagation path, and intelligent heuristics to guide and accelerate the decision-making process for deterministic automatic test pattern generation (ATPG). Essential is based on the well-known method of reverse time processing, but it applies forward processing within time frames to avoid disadvantageous a priori determination of a path to be sensitized or of a primary output to which the fault effects must be propagated. It is designed to exploit fully the sophisticated techniques used for combinational circuits in the Socrates ATPG system. Experimental results for sequential ATPG obtained with Essential (implemented in C on a Sequent Symmetry computer) are reported.<> View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty