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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 2003

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Displaying Results 1 - 23 of 23
  • The 2002 Symposium on VLSI Circuits - IEEE Journal of Solid-State Circuits

    Publication Year: 2003 , Page(s): 1 - 4
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    Freely Available from IEEE
  • Guest Editorial

    Publication Year: 2003 , Page(s): 687
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    Freely Available from IEEE
  • A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique

    Publication Year: 2003 , Page(s): 839 - 842
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (717 KB) |  | HTML iconHTML  

    This work describes an aggressive SRAM cell configuration using dual-VT and minimum channel length to achieve high performance. A bitline leakage reduction technique is incorporated into an L1 cache design using the new cell in a 100-nm dual-VT technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6-GHz operation at with 15% higher energy. View full abstract»

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  • A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

    Publication Year: 2003 , Page(s): 747 - 754
    Cited by:  Papers (44)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1668 KB) |  | HTML iconHTML  

    This paper describes the design and implementation of a quad high-speed transceiver cell fabricated in 0.13-μm CMOS technology. The clocking circuit of the cell employs a dual-loop architecture with a high-bandwidth core phase-locked loop (PLL) and low-bandwidth digitally controlled interpolators. To achieve low jitter while maintaining low power consumption, the dual-loop PLL uses two on-chip linear regulators of different bandwidths, one for the core and the other for the interpolator loop. The prototype chip operates from 400 Mb/s to 4 Gb/s with a bit error rate of <10-14. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400-mV output swing driving double terminated links. View full abstract»

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  • A ferroelectric memory-based secure dynamically programmable gate array

    Publication Year: 2003 , Page(s): 715 - 725
    Cited by:  Papers (12)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1441 KB) |  | HTML iconHTML  

    A nonvolatile ferroelectric memory-based eight-context dynamically programmable gate array (DPGA) enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories as well as the multicontext architecture. Since read and program sequences of configuration data loading from/to the DPGA are securely protected, unauthorized users cannot access the stored configuration data. The associated configuration memory consists of a SRAM-based six-transistor and 4-ferroelectric capacitor cell. The developed configuration memory achieves access time of 4ns, comparable to standard SRAM, which is 20 times faster than conventional ferroelectric memory; furthermore, it features a nondestructive read operation and a stable data recall scheme. The employed logic block circuit can effectively improve the available number of logic gates for the multicontext scheme with minimum area overhead. The prototype nonvolatile DPGA is fabricated in a 0.35-μm CMOS with ferroelectric memory technology, and the implementation result of the Data Encryption Standard (DES) encryption/decryption functions on this DPGA presents proper operation up to 51 MHz at 3.3V. The nonvolatile storage of configuration memory is verified for power-supply voltage as low as 1.5 V at room temperature, which is the lowest operation voltage ever reported for PbZrTiO3 (PZT)-based ferroelectric memories. View full abstract»

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  • A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

    Publication Year: 2003 , Page(s): 805 - 816
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (830 KB)  

    A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and ΣΔ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order ΣΔ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass ΣΔ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW. View full abstract»

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  • A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

    Publication Year: 2003 , Page(s): 734 - 740
    Cited by:  Papers (30)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (739 KB)  

    Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-μm CMOS logic processes. We trim the static integral nonlinearity to ±0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm2 of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s. View full abstract»

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  • Forward body bias for microprocessors in 130-nm technology generation and beyond

    Publication Year: 2003 , Page(s): 696 - 701
    Cited by:  Papers (48)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (710 KB) |  | HTML iconHTML  

    Device and test chip measurements show that forward body bias (FBB) can be used effectively to improve performance and reduce complexity of a 130-nm dual-VT technology, reduce leakage power during burn-in and standby, improve circuit delay and robustness, and reduce active power. FBB allows performance advantages of low-temperature operation to be realized fully without requiring transistor redesign, and also improves VT variations, mismatch, and saturation transconductance and output resistance product (gm×ro). View full abstract»

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  • A low-power 200-MHz receiver for wireless hearing aid devices

    Publication Year: 2003 , Page(s): 793 - 804
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1242 KB)  

    The design of a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8-μm BiCMOS technology is shown. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 μA is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude. View full abstract»

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  • Threshold-voltage balance for minimum supply operation [LV CMOS chips]

    Publication Year: 2003 , Page(s): 830 - 833
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (426 KB) |  | HTML iconHTML  

    The difference between the threshold voltages Vt of pMOS and nMOS transistors is a critical issue in the low-voltage operation of CMOS circuits. The pMOS/nMOS Vt balancing profit is analyzed in terms of subthreshold leakage current and the performance of CMOS LSIs and the minimum supply voltage of logic circuits. Matching the pMOS/nMOS Vt improves LSI performance and reduces the lowest supply voltage by 0.15 V. We propose a new concept of body bias management that uses forward biasing, fluctuation compensating, and Vt matching technologies to resolve the issue. View full abstract»

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  • Near speed-of-light signaling over on-chip electrical interconnects

    Publication Year: 2003 , Page(s): 834 - 838
    Cited by:  Papers (60)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    The propagation limits of electrical signals for systems built with conventional silicon processing are explored. A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light. In a 0.18-μm six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated. This approach offers a five times improvement in delay over a conventional repeater-insertion strategy. View full abstract»

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  • A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects

    Publication Year: 2003 , Page(s): 769 - 773
    Cited by:  Papers (47)  |  Patents (34)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB) |  | HTML iconHTML  

    A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm2 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-μm CMOS process utilizing five layers of metal and two layers of poly. View full abstract»

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  • A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

    Publication Year: 2003 , Page(s): 689 - 695
    Cited by:  Papers (37)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB) |  | HTML iconHTML  

    This paper describes a 32-bit address generation unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-VT semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend. View full abstract»

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  • A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer

    Publication Year: 2003 , Page(s): 741 - 746
    Cited by:  Papers (27)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (575 KB) |  | HTML iconHTML  

    The frequency-dependent attenuation of the transmission lines between chips and printed circuit boards, for example, is an obstacle to improving the performance of a system enhanced with LSI technology scaling. This is because large frequency-dependent attenuation results in poor eye-opening performance and a high bit-error rate in data transmission. This paper presents a 5-Gb/s 10-m 28AWG cable transceiver fabricated by using 0.13-μm CMOS technology. In this transceiver, a continuous-time post-equalizer, with recently developed no-feedback-loop high-speed analog amplifiers, can handle up to 9dB of frequency-dependent attenuation in cables and also achieve an 18-dB improvement in the attenuation (27dB total improvement) by using pre- and post-equalization techniques in combination. View full abstract»

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  • Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology

    Publication Year: 2003 , Page(s): 702 - 708
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (502 KB)  

    The impact of crosstalk on delay was examined by measuring a test chip manufactured with a 0.13-μm node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: 1) consideration of degradation change dependent on relative signal arrival time over a wide range; 2) static timing analysis-based operation; and 3) quantitative estimation of the degradation accumulation caused by multiple aggressors. A candidate for such simulation technology is provided, and its highly precise characteristics are demonstrated through comparisons between measurement and simulation. In a test structure with two aggressors, the maximum error between the measured and simulated degradation was reduced to less than one-sixth of that with a conventional method. View full abstract»

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  • Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

    Publication Year: 2003 , Page(s): 826 - 829
    Cited by:  Papers (50)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (505 KB) |  | HTML iconHTML  

    Adaptive supply voltage as well as adaptive body bias may be used to control the frequency and leakage distribution of fabricated microprocessor dies. Test chip measurements show that adaptive VCC is effective in reducing the impact of parameter variations on frequency, active power, and leakage power of microprocessors when 20 mV VCC resolution is used. Using adaptive VCC together with adaptive VBS or within-die body bias is much more effective than using any of them individually. View full abstract»

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  • A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-μm CMOS

    Publication Year: 2003 , Page(s): 782 - 792
    Cited by:  Papers (34)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (908 KB) |  | HTML iconHTML  

    A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-μm CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc. View full abstract»

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  • A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

    Publication Year: 2003 , Page(s): 762 - 768
    Cited by:  Papers (36)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (671 KB) |  | HTML iconHTML  

    A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-μm 126.5-mm2 512-Mb chip. View full abstract»

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  • A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications

    Publication Year: 2003 , Page(s): 817 - 825
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (964 KB) |  | HTML iconHTML  

    This paper describes a single-chip RF transceiver LSI for 2.4-GHz-band Gaussian frequency shift-keying applications, such as Bluetooth. This chip uses a 0.18-μm bulk CMOS process for lower current consumption. The LSI consists of almost all the required RF and IF building blocks: a transmit/receive antenna switch, a power amplifier, a low noise amplifier, an image rejection mixer, channel-selection filters, a limiter, a received signal strength indicator, a frequency discriminator, a voltage controlled oscillator, and a phase-locked loop synthesizer. The bandpass filter for channel selection was difficult to achieve since it operates at a low supply voltage. However, because large interference is roughly rejected at the output of the image rejection mixer and a wide-input-range bandpass filter with an optimized input bias is realized, the transceiver can operate at a supply voltage of 1.8 V. In the IF section, we adopted a circuit design using the minimum number of passive elements, resistors and capacitors, for a lower chip area of 10.2 mm2. View full abstract»

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  • A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture

    Publication Year: 2003 , Page(s): 726 - 733
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1311 KB) |  | HTML iconHTML  

    A still-image encoder based on vector quantization (VQ) has been developed using 0.35-μm triple-metal CMOS technology for encoding a high-resolution still image. The chip employs the needless calculation elimination method and the adaptive resolution VQ (AR-VQ) technique. The needless calculation elimination method can reduce computational cost of VQ encoding to 40% or less of the full-search VQ encoding, while maintaining the accuracy of full-search VQ. AR-VQ realizes a compression ratio of over 1/200 while maintaining image quality. The processor can compress a still image of 1600×2400 pixels within 1 s and operates at 66 MHz with power dissipation of 660 mW under 2.5-V power supply, which is 1000 times larger performance per unit power dissipation than the software implementation on current PCs. View full abstract»

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  • A highly integrated analog front-end for 3G

    Publication Year: 2003 , Page(s): 774 - 781
    Cited by:  Papers (9)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (686 KB) |  | HTML iconHTML  

    This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-μm (SOC) flash+logic+analog (FLA) process technology using a 0.35-μm feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm2. View full abstract»

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  • A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

    Publication Year: 2003 , Page(s): 755 - 761
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-VTH CMOS technology. The local bitline uses a leakage-tolerant self reverse-bias (SRB) scheme with nMOS source-follower pullup access transistors, while preserving robust full-swing operation. Gate-source underdrive of -220 mV on the bitline read-select transistors is established without external bias voltages or gate-oxide overstress. Device-level measurements in the 130-nm technology show 72× bitline active leakage reduction, enabling low-VTH usage, 40% bitline keeper downsizing, and 16 bitcells/bitline. 11% faster read delay and 2× higher dc noise robustness are achieved compared with high-performance dual-VTH bitline scheme. Sustained performance and robustness benefits of the SRB technique against conventional dynamic bitline with scaling to 100- and 70-nm technology is also presented. View full abstract»

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  • A transition-encoded dynamic bus technique for high-performance interconnects

    Publication Year: 2003 , Page(s): 709 - 714
    Cited by:  Papers (17)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short-length buses, while obtaining energy savings at aggressive delay targets. On a 180-nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement using this technique. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan