By Topic

Circuits and Systems, IEEE Transactions on

Issue 6 • Date June 1991

Filter Results

Displaying Results 1 - 17 of 17
  • Comments, with reply, on "Chaos from third-order phase-locked loops with a slowly varying parameter" by Y.-H. Chu et al

    Publication Year: 1991 , Page(s): 677 - 678
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    The commenter refers to a third-order nonautonomous differential equation rewritten as a set of three first-order equations used in the work of Y.-H. Chu et al. (see ibid., vol.37, p.1104-15, 1990). He points out inconsistencies in the use of the a' and k parameters. In their reply, the authors clarify their position and mention that some explanatory material should have been included in the commented paper to avoid the readers' confusion.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic range, stability, and fault-tolerant capability of finite-precision RLS systolic array based on Givens rotations

    Publication Year: 1991 , Page(s): 625 - 636
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    The QR decomposition recursive least-squares (QRD RLS) algorithm for mapping onto a systolic array for signal processing and communication applications is considered. Detailed analysis is presented to show that the rotation parameters of the RLS algorithm based on the Givens rotation method will eventually reach the quasi-steady-state if the forgetting factor λ is very close to 1. With this model, the dynamic range of each processing cell can be derived, and from this a proper wordlength can be chosen to ensure correct operation of the algorithm. The proposed solutions are simple and effective. Simulations have demonstrated that the wordlengths chosen by the proposed dynamic range work well. The stability of the QRD RLS algorithm is demonstrated under a finite-precision implementation with this observation. Finally, the missing error detection and false alarm problems are considered based on the results obtained from the model. The wordlength is overflow-free without missing error detection and false alarm problems. The results in this study are of practical importance. Not only can a finite-precision QRD RLS systolic array be designed with a minimum wordlength that ensures correct operations, but also a fault-tolerant system that can detect a given error size and is false-alarm-free under the quantization effect can be provided View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analog floating-gate synapses for general-purpose VLSI neural computation

    Publication Year: 1991 , Page(s): 654 - 658
    Cited by:  Papers (29)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    A floating-gate-based synapse structure for neural computing fabricated by a standard double-polysilicon CMOS process is presented. Simulation and experimental results on conductance programmability and charge retention demonstrate the capability of this programmable synapse circuit. With this circuit a neural chip of 100K synapses complexity can be constructed using one megabit static-RAM fabrication technologies View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the synthesis of multidimensional reactance multiports

    Publication Year: 1991 , Page(s): 637 - 642
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    Multidimensional lossless networks are of interest, for example, for use as reference filters for multidimensional wave digital filters. Necessary properties of the scattering matrix of such multiports have been established. In the design of k-dimensional reactance networks it is of great interest whether these mentioned features are also sufficient for a given matrix to be the scattering matrix of such a system, or not. It is shown that this is not the case for dimensions greater than two. Hence, no general synthesis procedure for multidimensional reactance multiports exists, as is in the one- and two-dimensional cases View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Partial fraction expansion without derivative evaluation

    Publication Year: 1991 , Page(s): 658 - 660
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    A practical algorithm for computing the partial fraction expansion of a general rational function without derivative evaluations is given. In addition, it is shown how to reduce the roundoff error in its implementation. The procedure is rather straightforward, accurate, efficient, and easy to program View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel approach to the synthesis of recursive digital filters with linear phase

    Publication Year: 1991 , Page(s): 602 - 612
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (820 KB)  

    The synthesis of recursive digital filters with linear phase is approached by means of existing approximation techniques. The design is based on a finite impulse response (FIR) filter that represents the ideal filter in terms of both magnitude and phase characteristics. The recursive digital filter with linear phase is then synthesized as an approximation of the FIR model where optimal Hankel approximation theory as well as the model reduction techniques are used. The causality and stability of the designed filter are guaranteed. This technique is used for designing both one-dimensional and two-dimensional recursive digital filters with linear phase, and is illustrated by a few numerical examples View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design methodology of CMOS algorithmic current A/D converters in view of transistor mismatches

    Publication Year: 1991 , Page(s): 660 - 667
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    The CMOS algorithmic current A/D converter is analyzed. with emphasis on the modeling and quantitative description that relate the accuracy of the converter to the transistor mismatch and the reference current of the converter. This leads to an inequality for determining the optimum sizes of the devices and the value of the reference current. It is shown that the area of the converter can be significantly reduced by scaling the devices per stage, without loss of accuracy and without an increase of the reference current. Design strategies of the converter are demonstrated by an example for an 8-b A/D converter. Inherent error sources such as offset and glitching are also considered. Simple means to solve these problems are proposed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A model for estimating power dissipation in a class of DSP VLSI chips

    Publication Year: 1991 , Page(s): 646 - 650
    Cited by:  Papers (25)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    A high-level power dissipation model for filter- and transform-type digital signal processing (DSP) algorithms implemented using linearly connected multiply-add-based processing elements is presented. Exploration of alternative algorithms, architectures, and design styles for a given signal processing task in terms of high-level parameters is possible using this model. It is shown that there is often an optimal selection of the number and type of time-shared processing elements for VLSI implementation that minimizes the overall power dissipation. A major application of the proposed model is to make quantitative evaluations for exploration of alternative DSP algorithms and architectures. When combined with previously developed area-time metrics, the proposed power dissipation model permits a more realistic evaluation of new and existing circuit solutions to DSP tasks View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel analog to digital converters using voltage inverter switches. I. Reference circuits

    Publication Year: 1991 , Page(s): 582 - 589
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    Novel analog to digital converter (ADC) circuits that incorporate voltage inverter switches (VISs) are described. In the first part the principles of voltage inversion are described. It is shown how these circuits can be used to construct very accurate divide-by-two reference circuits. Due to the ability of the VIS circuits to compensate for parasitic losses during the process of capacitor charge redistribution, these reference circuits are superior to previous designs. Three different VIS reference circuits are presented. Theoretical analyses are confirmed with computer simulations and measured results from experimental circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wirability of knock-knee layouts with 45° wires

    Publication Year: 1991 , Page(s): 613 - 624
    Cited by:  Papers (7)  |  Patents (96)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    The problem of wiring an arbitrary knock-knee layout (in a square grid with an arbitrary number of modules) in three and two layers using a small number of vias is investigated. A technique is proposed for transforming a knock-knee layout into a three-layer wirable layout by replacing knock-knees with 45° wires. A 45° replacing algorithm to achieve three-layer wirability is introduced. An efficient stretching technique to ensure two-layer wirability using 45° wires is described. Conversion of an abstract layout into a corresponding physical layout is discussed. Experimental results are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Different classes of diagnosable systems: relationship and common diagnosis algorithm

    Publication Year: 1991 , Page(s): 642 - 645
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    In the literature on diagnosable systems it has been shown that several subclasses of systems that can be diagnosed more efficiently than the general case exist. Some of these subclasses are D(n.t,X) systems introduced by K.Y. Chwa et al. (1981), self-implicating systems (A.T. Dahbura et al., 1985), and systems with connection assignment digraph of node connectivity t (G.F. Sullivan, 1978, S.L. Hakimi et al., 1974). The relationship between these classes is investigated and a diagnosis algorithm that is applicable to systems belonging to any of these classes is formulated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Decomposition of binary integers into signed power-of-two terms

    Publication Year: 1991 , Page(s): 667 - 672
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    Previous work has shown that approximation of digital filter coefficients using sums of signed power-of-two terms yields significant area/speed advantages in custom implementations, at the expense of a slight frequency response deterioration. The completeness, uniqueness, and resolving power of signed powers-of-two representations are studied, and circuits for extracting a prescribed number of signed power-of-two terms whose sum is the closest approximation to a given integer are presented. Examples of implementation of these circuits in a CMOS process are given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stability of cellular neural networks with opposite-sign templates

    Publication Year: 1991 , Page(s): 675 - 677
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    Cellular neural networks (CNNs) with opposite-sign templates have been successfully applied by T. Matsumoto et al. in connected component detection (CCD) in feature extraction (see ibid., vol.37, p.633-5, 1990). A stability analysis of this class of nonreciprocal CNN is provided by L.O. Chua et al. (see ibid., vol.37, p.1520-7, 1990). In this paper, a thorough stability analysis of this type of CNNs which shows the dependence of complete stability on the template values is presented. Parameter regions for complete stability and instability are determined, and the parameter region for the functionality of CCD is also given based on this investigation. Simulation examples verify that the complete stability of CNN with opposite-sign templates is not always preserved View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • RL-multivibrator and retrieving the coil magnetization curve

    Publication Year: 1991 , Page(s): 650 - 653
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A method for retrieving the magnetization curve of a nonlinear coil is described. The parameters of a piecewise-linear or a third-order polynomial approximation can be obtained. A simple bridge RL-multivibrator, which includes an operational amplifier and this coil, is used. The coil parameters are calculated observing two oscillograms of the voltage at one of the bridge branches and measuring the oscillation period View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient algorithmic decomposition of transistor groups into series, bridge, and parallel combinations

    Publication Year: 1991 , Page(s): 569 - 581
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1308 KB)  

    A novel approach to automatically decompose MOS transistor groups into pull-up, pull-down, and pass-transistor subgroups is described. The subgroups are further recursively decomposed into series, parallel, and bridge combinations, all in linear time. This approach is more powerful and efficient than existing ones and has important applications in static timing analysis, electrical verification, and simulation of MOS VLSI digital circuits. It has been implemented and tested in the timing analysis program TAMIA and requires as little as 0.0025 s/transistor to decompose a large circuit on a SUN3 computer View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A digital differential-line receiver for CMOS VLSI currents

    Publication Year: 1991 , Page(s): 673 - 675
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    Interferences due to parasitic capacitances between close circuits leading to undesired logic behaviors in VLSI circuits are considered. A CMOS differential-line receiver is proposed to avoid the effect of these perturbances. The receiver reaches a differential and common-node noise immunity which is higher than the circuit power supply voltage View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of floating point roundoff errors using dummy multiplier coefficient sensitivities

    Publication Year: 1991 , Page(s): 590 - 601
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (956 KB)  

    A simple method for analyzing roundoff errors in floating-point digital filters is presented. The method is based on the coefficient sensitivities of dummy multipliers with gains of one and connects the roundoff error analysis to coefficient sensitivity analysis. A general formulation for calculating the roundoff noise level at the output of a digital filter is presented, and a simple upper bound for roundoff error accumulation is derived. The approach makes it possible to draw some general conclusions about the floating-point roundoff noise properties of certain filter structures. The cascade, parallel, and Gray-Markel lattice structures are analyzed in detail. The interaction between coefficient sensitivity and roundoff error is discussed, and several general conclusions are drawn. Numerical examples confirm that the method is accurate enough for practical use View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.