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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Issue 4 • Date Apr 2003

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Displaying Results 1 - 8 of 8
  • 1.5-V CMOS CCII+ with high current-driving capability

    Publication Year: 2003, Page(s):187 - 190
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (615 KB) | HTML iconHTML

    A novel CMOS low-voltage positive current conveyor of second generation is described in this paper. This solution allows almost rail-to-rail input and output operation and a high driving capability, thanks to the adoption of a class AB current output stage. A prototype was fabricated in a 0.35-μm technology and experimentally tested. Using a 1.5-V supply, the circuit exhibited an input resistan... View full abstract»

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  • A current mirroring integration based readout circuit for high performance infrared FPA applications

    Publication Year: 2003, Page(s):181 - 186
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (515 KB) | HTML iconHTML

    Reports a current mirroring integration (CMI) CMOS readout circuit for high-resolution infrared focal plane array (FPA) applications. The circuit uses a feedback structure with current mirrors to provide stable bias voltage across the photodetector diode, while mirroring the diode current to an integration capacitor. The integration capacitor can be placed outside of the unit pixel, reducing the p... View full abstract»

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  • A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

    Publication Year: 2003, Page(s):191 - 195
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (811 KB) | HTML iconHTML

    An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is p... View full abstract»

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  • An approach to tackle quantization noise folding in double-sampling ΣΔ modulation A/D converters

    Publication Year: 2003, Page(s):157 - 163
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB) | HTML iconHTML

    ΣΔ-modulation is a proven method to realize high- and very high-resolution analog-to-digital converters. A particularly efficient way to implement such a modulator uses double-sampling where the circuit operates during both clock phases of the master-clock. Hence, the sampling frequency is twice the master-clock frequency. Unfortunately, path mismatch between both sampling branches cau... View full abstract»

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  • Extended Hebbian learning for blind separation of complex-valued sources

    Publication Year: 2003, Page(s):195 - 202
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (507 KB) | HTML iconHTML

    The aim of this work is to present a nonlinear extension to Sanger's generalized Hebbian learning algorithm for complex-valued signal processing by neural networks. A possible choice of the involved nonlinearity is discussed by recalling the Sudjianto-Hassoun interpretation of nonlinear Hebbian learning. An extension of this interpretation to the complex-valued case leads to a Rayleigh nonlinearit... View full abstract»

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  • On the design of adjustable fractional delay FIR filters

    Publication Year: 2003, Page(s):164 - 169
    Cited by:  Papers (70)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB) | HTML iconHTML

    This brief considers minimax design of adjustable fractional delay finite-impulse response (FIR) filters. We employ a filter structure that, in the paper by Vesma and Saramaki in 1997, is referred to as the modified Farrow structure which makes use of a number of linear-phase FIR subfilters. Previously, only the cases where all subfilters are of equal order have been considered. In this brief, we ... View full abstract»

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  • Generic SoC QR array processor for adaptive beamforming

    Publication Year: 2003, Page(s):169 - 175
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (602 KB) | HTML iconHTML

    A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create... View full abstract»

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  • A hybrid ΔΣ fractional-N frequency synthesizer

    Publication Year: 2003, Page(s):176 - 180
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB) | HTML iconHTML

    Proposes a new frequency synthesizer architecture which uses a combination of known techniques. The architecture is evaluated by simulation and shown to reduce spurious content of existing fractional-N synthesizers. It also allows arbitrarily small channel spacing with existing fractional-N synthesizers. View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope