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Circuits, Devices and Systems, IEE Proceedings -

Issue 1 • Date Feb 2003

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Displaying Results 1 - 13 of 13
  • Phase noise contribution of the phase/frequency detector in a digital PLL frequency synthesiser

    Publication Year: 2003 , Page(s): 1 - 5
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (375 KB)  

    A theoretical basis for the figure of merit method used to quantify the phase noise plateau of a PLL frequency synthesiser is described. Analyses are developed both to calculate the in-band phase noise of a given synthesiser architecture and to predict the figure of merit from the phase/frequency detector parameters. A range of experimental results is provided to validate the theory. View full abstract»

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  • Optimisation techniques for reducing global bus switching activity in realisations of sum-of-products computations in DSP systems

    Publication Year: 2003 , Page(s): 16 - 26
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    Optimisation techniques aiming at the reduction of power consumption in digital signal processing (DSP) systems are presented. These optimisation techniques hold for all algorithms, including sum-of-products computations between input data and coefficients, which is a very broad category of DSP algorithms. Power savings are obtained through the reduction of switching activity in both (input and coefficient) data and address buses of the hardware architecture implementing the algorithm. The reduction of switching activity is obtained by means of a shuffling of the sequence, in which the partial products required by the sum-of-products computations are executed. The optimisation problems are formulated as travelling salesman problem (TSP) instances, which is a well known NP-complete problem. The cost function that drives the optimisation process takes explicitly into consideration addressing-related issues, which is not the case in existing approaches dealing with the same problem. Experimental results show that the proposed techniques achieve significant switching activity savings, resulting in corresponding power savings, while ensuring that no penalties are introduced in the address buses. View full abstract»

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  • Global performance evaluation of various on-chip square spiral inductors on GaAs substrates

    Publication Year: 2003 , Page(s): 51 - 56
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (359 KB)  

    Experimental and simulation results are presented for the performance evaluation of various on-chip spiral inductors on GaAs substrates. These inductors were fabricated with different track widths and turn numbers, but identical track spacing. Based on the proposed equivalent lumped circuit model for the inductors and the experimental de-embedded S-parameters, the inductance, Q-factor, self-resonance frequency, and figure-of-merit indicator of these inductors are determined. Excellent agreement between measurement and simulation results is achieved. Some local scalable formulas are obtained to describe the global performance of these inductors. View full abstract»

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  • Enhanced numerical modelling of non-cooled long-wavelength multi-junction (Cd,Hg)Te photodiodes

    Publication Year: 2003 , Page(s): 65 - 71
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (514 KB)  

    The theoretical analysis of long wavelength uncooled photovoltaic devices based on complex two-dimensional Hg1-xCdxTe heterostructures is presented. An enhanced computer program has been developed to solve the system of nonlinear continuity equations and the Poisson equation. All physical quantities of semiconductor structure are expressed as functions of electric potential and Fermi quasi-levels. The noise analysis is based on the set of 'transport equations for fluctuations' that enables calculations of spatial distribution of electrical potential and Fermi quasilevel fluctuations. Both generation recombination noise and If noise caused by mobility fluctuations were taken into account. The results of calculations are presented as maps illustrating spatial distributions of current densities, electrical gain, and fluctuations of selected physical quantities. Detectivity of 4×107 cmHz12/W-1 is predicted for a 10.6 μm unbiased multiple heterojunction photovoltaic device with 20 μm period. The theoretical predictions have been compared with performance of practical devices. View full abstract»

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  • Versatile driving system for non-root-mean-square responding liquid crystal displays

    Publication Year: 2003 , Page(s): 57 - 62
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (489 KB)  

    The authors present a versatile stand-alone driving system specially designed for addressing non-root-mean-square responding liquid crystal displays. It is suitable for driving surface stabilised ferroelectric, antiferroelectric and zenithal bistable nematic liquid crystal test displays. The system has sixty-four channels with nearly 140 V swing for row driving and sixty-four channels with 50 V swing for column driving, and can drive displays with 64 rows and 64 columns and emulate matrix addressing of up to 16 384 rows at video rate. It has been successfully used for driving ferroelectric and antiferroelectric liquid crystal displays. View full abstract»

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  • Mixed-level hierarchical analogue modelling

    Publication Year: 2003 , Page(s): 78 - 84
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    A CAD tool is introduced that provides the facility to model an analogue circuit in a way that fully exploits hierarchical structure and mixed levels of abstraction. MGAM (model generator for analogue macros) provides the designer with the capacity to adjust model complexity, allowing a trade-off between simulation time and accuracy. MGAM comprises three key functions: (i) high-level model generation from a circuit-level description of an analogue module, (ii) the ability to support hierarchical modelling, using mixed-level models, and (iii) the capacity to vary the complexity of the models to meet specified accuracy targets. View full abstract»

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  • Editorial - Device modelling for circuits, components and systems

    Publication Year: 2003 , Page(s): 63 - 64
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (227 KB)  

    First Page of the Article
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  • Analysis of mirror mismatch and clock-feedthrough in Bruton transformation switched current wave filters

    Publication Year: 2003 , Page(s): 6 - 15
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (587 KB)  

    The paper describes the modelling and analysis of the non-ideal performance of recently introduced Bruton transformation switched current (SI) wave filters. Two sources of errors are considered: mismatching in current mirrors and clock-feedthrough in delay cells. Using transistor-level realisations, analytical non-ideal models for the main components of Bruton transformation wave filters are developed, including capacitive source and load, and frequency dependent negative resistors. These models are integrated with MATLAB to study the influence of these errors on the filter frequency response. The non-ideal performance of 3rd-order low-pass and 5th-order high-pass elliptic filters using second-generation and S2I delay cells are analysed and included. View full abstract»

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  • Sensitivity of embedded component temperature to PCB structure and heat transfer coefficient

    Publication Year: 2003 , Page(s): 73 - 77
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    The sensitivity of embedded component temperature to the location of an embedded copper ground plane is investigated using computer simulation. The results show that the presence of a copper ground plane in close proximity to a component layer improves the potential packing density of components within the layer. Furthermore, placing a copper ground plane between two signal layers can reduce thermal interaction between components in the two layers by a factor of up 10. The layer density within a multilayer PCB is therefore improved, which again leads to a higher packing density of components. Using the results generated by the simulation, the authors then proceed to investigate the sensitivity of embedded resistor temperature to resistor size under different conditions of surface heat transfer. The results show that large embedded resistors are more sensitive to surface heat transfer than smaller ones and that small components are more effectively cooled by placing embedded copper ground planes in close proximity to them. View full abstract»

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  • HDL-based methodology for VLSI design of AC motor controller

    Publication Year: 2003 , Page(s): 38 - 44
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    The authors present a methodology for designing a CMOS very large scale integration (VLSI) controller for AC motor control. Step-by-step, top-down methodology based on hardware description languages (HDL) with mixed simulation was used to study digital adaptation and architecture implementation of the control algorithm. An application using the proposed methodology was studied: the direct torque control (DTC) of an AC motor. The DTC is described and VLSI examined. Analogue and digital models were used to describe the algorithm implementation, specific binary format and architecture. The register transfer level (RTL) model for the DTC controller was validated by mixed simulation. The ASIC layout was created using Austria Mikro System standard cell library for 0.8 μm CMOS. Finally, the authors compared this VLSI approach with software implementation and co-design methodology. View full abstract»

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  • Bounding integrator output of sigma-delta modulator by time delay feedback control

    Publication Year: 2003 , Page(s): 31 - 37
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (570 KB)  

    Internal integrator saturation is one of the practical problems arising in second- and high-order sigma-delta modulators (SDMs). It has been avoided by scaling integrator gains, feedback coefficients and other circuit parameters. In the paper, a novel compensation technique has been introduced to keep the signal levels throughout the modulator below saturation limits most of the time. The technique is based on feedback compensation and contains a delay element and a feedback gain and is employed for sigma-delta modulators by use of the unquantised output signal alone. The technique can readily be applied to various configurations of oversampling converters, single-loop and multiple-loop structures, and improves their stability. View full abstract»

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  • CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI

    Publication Year: 2003 , Page(s): 45 - 50
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (438 KB)  

    The paper describes a differential CMOS logic family employing self-timing for speed enhancement and charge recycling for power reduction. The logic family is up to 49% faster than other types of dynamic circuits. A pseudo one-phase clocking pipeline configuration implemented with the proposed logic family can boost clock frequency by eliminating latching stages between pipeline sections. A 64-bit adder designed using the proposed logic family achieves 0.97 ns latency with power dissipation comparable to that of the conventional precharged differential logic family. View full abstract»

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  • Floating operational transconductance amplifier based grounded impedance

    Publication Year: 2003 , Page(s): 27 - 30
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (334 KB)  

    A technique to reproduce, in floating form, a given operational transconductance amplifier (OTA) based grounded impedance (GI) is presented. Unlike the back-to-back technique, the technique presented has the feature that the required additional matching constraints (i.e. in addition to those, if any, in the given GI) are independent of the original components, implying that the canonicity with regard to the number of capacitors and the single-element tunability, if any, in the given GI are fully retained in the resulting floating impedance. View full abstract»

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