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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date April 2003

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Displaying Results 1 - 15 of 15
  • Guest editorial

    Page(s): 385 - 386
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    Freely Available from IEEE
  • An effective congestion-driven placement framework

    Page(s): 387 - 394
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (831 KB) |  | HTML iconHTML  

    We present a fast but reliable way to detect routing criticalities in very large scale integration chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a postplacement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1300000 cells are presented. The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average. View full abstract»

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  • Twin binary sequences: a nonredundant representation for general nonslicing floorplan

    Page(s): 457 - 469
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    The efficiency and effectiveness of many floorplanning methods depend very much on the representation of the geometrical relationship between the modules. A good representation can shorten the searching process so that more accurate estimations on area and interconnect costs can be performed. Nonslicing floorplan is the most general kind of floorplan that is commonly used. Unfortunately, there is not yet any complete and nonredundant topological representation for nonslicing structure. In this paper, we propose the first representation of this kind. Like some previous work (Zhou et al. 2001), we have also made use of a mosaic floorplan as an intermediate step. However, instead of including a more than sufficient number of extra dummy blocks in the set of modules (that will increase the size of the solution space significantly), our representation allows us to insert an exact number of irreducible empty rooms to a mosaic floorplan such that every nonslicing floorplan can be obtained uniquely from one and only one mosaic floorplan. The size of the solution space is only O(n!23n/n1.5), which is the size without empty room insertion, but every nonslicing floorplan can be generated uniquely and efficiently in linear time without any redundant representation. View full abstract»

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  • Routability-driven floorplanner with buffer block planning

    Page(s): 470 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (830 KB) |  | HTML iconHTML  

    In traditional floorplanners, area minimization is an important issue. However, due to the recent advances in very large scale integration technology, the number of transistors in a design are increasing rapidly and so are their switching speeds. This has increased the importance of interconnect delay and routability in the overall performance of a circuit. We should consider interconnect planning, buffer planning, and routability as early as possible. In this paper, we study and implement a routability-driven floorplanner with congestion estimation and buffer planning. Our method is based on a simulated annealing approach that is divided into two phases: the area optimization and congestion optimization phases. In the area optimization phase, modules are roughly placed according to the total area and wirelength. In the congestion optimization phase, a floorplan is evaluated by its area, wirelength, congestion, and routability. We assume that buffers should be inserted at flexible intervals from each other for long enough wires and probabilistic analysis is performed to compute the congestion information taken into account the constraints in buffer locations. Our approach is able to reduce the average number of wires at the congested areas and allow more feasible insertions of buffers to satisfy the delay constraints without having much penalty in increasing the area of the floorplan. View full abstract»

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  • Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

    Page(s): 481 - 491
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    We give an overview of a buffer tree synthesis package which pays particular attention to the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, congestion, exploitation of temporal locality among the sinks, and addressing sink polarity requirements. Experimental results demonstrate the effectiveness of the tool in comparison with previously proposed techniques. View full abstract»

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  • Timing-driven routing for FPGAs based on Lagrangian relaxation

    Page(s): 506 - 510
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    As interconnection delay plays an important role in determining circuit performance in field programmable gate arrays (FPGAs), timing-driven FPGA routing has received much attention recently. In this paper, we present a new timing-driven routing algorithm for FPGAs. The algorithm minimizes critical path delay for a given placed circuit using the Lagrangian relaxation technique. Lagrangian multipliers used to relax timing constraints are updated by subgradient method over iterations. Incorporated into the cost function, these multipliers guide the router to construct a routing tree for each net. During routing, the congestion constraints on each routing resource are also handled to route circuits successfully. Experimental results on benchmark circuits show that our approach outperforms the state-of-the-art versatile place and route router. View full abstract»

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  • Buffer insertion with adaptive blockage avoidance

    Page(s): 492 - 498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (677 KB) |  | HTML iconHTML  

    Buffer insertion is a fundamental technology for very large scale integration interconnect optimization. This work presents the repeater insertion with adaptive tree adjustment (RIATA) heuristic that directly extends van Ginneken's classic algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment adapts to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. RIATA can be combined with any performance-driven Steiner tree algorithm and permits various solution search schemes to achieve different solution quality and runtime tradeoffs. Experiments on several large nets confirms that high-quality solutions can be obtained through this technique with greater efficiency than simultaneous approaches. View full abstract»

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  • Multilevel global placement with congestion control

    Page(s): 395 - 409
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    In this paper, we develop a multilevel global placement algorithm (MGP) integrated with fast incremental global routing for directly updating and optimizing congestion cost during physical hierarchy generation. Fast global routing is achieved using a fast two-bend routing and incremental A-tree algorithm. The routing congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is developed for placing objects with significant size variations. Experimental results show that, compared to GORDIAN-L, the wire length-driven MGP is 4-6.7 times faster and generates slightly better wire length for test circuits larger than 100000 cells. Moreover, the congestion-driven MGP improves wiring overflow by 45%-74% with 5% larger bounding box wire length but 3%-7% shorter routing wire length measured by a graph-based A-tree global router. View full abstract»

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  • On integrating power and signal routing for shield count minimization in congested regions

    Page(s): 437 - 445
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    With worsening crosstalk in nanometer designs, it is increasingly important to control the switching cross-coupling experienced by critical wires. This is commonly done by inserting shields adjacent to these wires. However, the number of shielded wires can become extremely large, resulting in a large area impact. We address this problem at both the methodological and algorithmic levels, integrating the traditionally separate steps of power and signal routing in a safe manner to minimize the number of shields required to satisfy all shielding constraints. We propose a new abstraction for the block-level global and detailed routing hierarchy that allows accurate early estimation of crosstalk. Furthermore, we postpone the power routing in middle metal layers to after critical signal nets and their shields have been laid out (with maximal shield sharing), and then try to construct a fine-grained power grid out of the already routed shields. Given a routing on a metal layer, our adaptive power routing algorithm adds provably fewest new power lines to complete the power grid on that layer while guaranteeing adequate power delivery. Our approach has proven effective while designing some high-frequency blocks of a commercial gigahertz range microprocessor using a 0.18-μm process technology. View full abstract»

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  • Optimal decoupling capacitor sizing and placement for standard-cell layout designs

    Page(s): 428 - 436
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    With technology scaling, the trend for high-performance integrated circuits is toward ever higher operating frequency, lower power supply voltages, and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in application specific integrated circuit (ASIC)-like circuits. The problem is formulated as one of nonlinear optimization and is solved using a sensitivity-based quadratic programming (QP) solver. The adjoint sensitivity method is applied to calculate the first-order sensitivities. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change in the total chip area. View full abstract»

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  • Global and local congestion optimization in technology mapping

    Page(s): 498 - 505
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    In this era of deep submicrometer technologies, interconnects are becoming increasingly important as their effects strongly impact the integrated circuit (IC) functionality and performance. Moreover, logic block size is no longer determined exclusively by total cell area and is often limited by wiring area. However, synthesis optimization objectives are focused on minimizing the number and size of library cells. Methodologies that incorporate congestion within the logic synthesis objective function have been proposed in the past. Nevertheless, we will demonstrate that predicting the true congestion prior to layout is not possible, and the effectiveness of any congestion minimization approach can only be evaluated after routing is completed within the fixed die size. In this paper, we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the technology-dependent synthesis cost function and then applies incremental localized unmapping and remapping on layout congested areas. This complete approach addresses the problem that one global factor is not suited for all layout regions of the design, which might have very different routing demands. Most importantly, through the application of this methodology to industrial examples, we will show that any attempt at a purely top-down single-pass congestion-aware technology mapping is merely wishful thinking. View full abstract»

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  • Design hierarchy-guided multilevel circuit partitioning

    Page(s): 420 - 427
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    In this paper, we present a new multilevel circuit partitioning algorithm (dhml) which is guided by design hierarchy. In addition to flat netlist hypergraph, we use user design hierarchy as a hint for partitioning. This design hierarchy already has some implications on connectivity between logical blocks in the design. Using design hierarchy in partitioning is nontrivial since the hierarchical elements in design hierarchy do not necessarily have strong internal connectivity; hence, we need to determine whether it is preferable to break up or preserve the hierarchical elements. In order to identify and select the hierarchical elements with strong connectivity, their Rent exponents are used. Then, the selected hierarchical elements serve as effective clustering scopes during the multilevel coarsening phase. The scopes are dynamically updated (enlarged) while building up a clustering tree so that the clustering tree resembles the densely connected portions of the design hierarchy. We tested our algorithm on a set of large industrial designs in which the largest one has 1.8 million cells, 2.8 million nets, and 11 levels of hierarchy. By exploiting design hierarchy, our algorithm produces higher quality partitioning results than the state-of-the-art multilevel partitioner hMetis. Furthermore, experimental results show that dhml yields significantly more stable solutions, which is helpful in practice to reduce the number of runs to obtain the best result. View full abstract»

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  • Routability-driven white space allocation for fixed-die standard-cell placement

    Page(s): 410 - 419
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    The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement. In the top-down placement flow, white space is assigned to congested regions using smooth allocating functions. A post-allocation optimization step is taken to further improve placement quality. Experimental results show that the proposed allocation approach, combined with a multilevel placement flow, significantly improves placement routability and layout quality. A set of approaches for white space allocation has been presented and compared in this paper. All of them are based on routability-driven methods. However, these approaches vary in the allocation function and allocation aggressiveness. All the placement results are investigated by feeding them into a widely used industrial router (Warp Route of Cadence). Comparisons have been made between: 1) placement with or without white space allocation; 2) different white space allocation approaches; and 3) our placement flow, industrial placement tool, and the other state-of-the-art academic placement tool. View full abstract»

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  • TEG: a new post-layout optimization method

    Page(s): 446 - 456
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    Post-layout is an important stage in the modern very large scale integration (VLSI) design. In this stage, the extraction and verification tools can get the most accurate results with the complete layout information, and the layout problems can be detected precisely for further design improvements or optimizations. But the problem is that the design optimization is very hard to perform in post-layout. Every design modification is under tight geometry constraints. Usually the designer either changes layout manually by layout editor, or goes back to previous placement or routing stage in order to have the preferred results. How to modify the layout becomes a bottleneck in the post-layout optimization. In this paper, we propose a new method to resolve this problem called the triangulation encoding graph (TEG) method. Based on an improved topological layout representation and a set of layout operation algorithms, TEG provides an incremental layout modification environment for post-layout optimizations. Experimental results show that TEG is efficient and effective in processing industry VLSI designs. View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu