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Solid-State Circuits, IEEE Journal of

Issue 4 • Date April 2003

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Displaying Results 1 - 15 of 15
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  • A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

    Page(s): 594 - 602
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (629 KB) |  | HTML iconHTML  

    A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm2 including the bonding pads. View full abstract»

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  • A 0.18-μm CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter

    Page(s): 603 - 613
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (801 KB) |  | HTML iconHTML  

    A DCS1800 offset-phase-locked-loop upconversion modulation loop integrated circuit (IC) fabricated in a 0.18-μm CMOS technology is presented in this paper. This IC operates at 2.8-V supply voltage with a current consumption of 36 mA. The measured root-mean-square and peak phase errors of the Gaussian minimum shift keying (GMSK) transmission signal are 1.6° and 4°, respectively. It is shown that such circuits can be implemented in CMOS process with current dissipation and performance comparable to BiCMOS chips. Advantages of upconversion modulation loop and design issues of I/Q modulators are also described. View full abstract»

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  • Jitter transfer characteristics of delay-locked loops - theories and design techniques

    Page(s): 614 - 621
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (583 KB) |  | HTML iconHTML  

    This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first-order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated. View full abstract»

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  • A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance

    Page(s): 669 - 672
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB) |  | HTML iconHTML  

    A current-reused two-stage low-noise amplifier (LNA) topology is proposed, which adopts a series inter-stage resonance and optimized substrate resistance of individual transistors. The characteristics of the series inter-stage resonance in gain enhancement are analyzed and compared with other alternatives. The contradicting effects of substrate resistance on common-source and common-gate amplifiers are analyzed and proposed guidelines for high-gain operation. The LNA is implemented based on a 0.35-μm CMOS technology for 5.2-GHz wireless LAN applications. Measurements show 19.3dB of power gain, 2.45 dB of noise figure, and 13.2 dBm of output IP3, respectively, for the dc power supply of 8 mA and 3.3 V. View full abstract»

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  • Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

    Page(s): 622 - 630
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (470 KB) |  | HTML iconHTML  

    Interlocked pipelined CMOS (IPCMOS), a new asynchronous set of clock circuits suitable for high-frequency and low-power operation, is described. In IPCMOS, the reduced power results from enabling the local clocks only when there is an operation to perform and from a simple single-stage latch. The single-stage latch can be used because the locally generated clocks driving adjacent stages are not enabled simultaneously. The combination of enabling the clocks only when there is an operation to perform and the simple latch can lower power by a factor of five to ten times in many applications. In IPCMOS, the staggered local clocks also result in a significant reduction of dynamic Ldi/dt noise. In addition to the locally generated interlocked clocks and the single-stage latch, unique circuits that combine the function of a static NOR and an input switch are key to achieving high performance and minimizing the overhead in the interlocking. In a 0.18-μm bulk CMOS technology, these circuits drive a path through a typical 64-b multiplier stage at 3.3-4.5 GHz on an experimental chip. IPCMOS also provides a way to implement the interface between asynchronous and synchronous portions of a design, thereby giving the approach a great deal of flexibility by making it possible to drop IPCMOS into portions of an existing synchronous design. View full abstract»

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  • A fast multispeed comma-free Reed-Solomon decoder for W-CDMA applications using foldable systolic array architecture

    Page(s): 677 - 682
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    This brief proposes a fast multispeed comma-free Reed-Solomon (CFRS) decoder for the frame synchronization and code-group identification in the cell search of the Third Generation Partnership Project wide-band code-division multiple access/frequency division duplexing (W-CDMA/FDD) system. A foldable systolic array is proposed to achieve fast decoding and provide flexible tradeoffs between power consumption, chip size, and decoding latency. Multispeed decoding, an idea that is useful for cell search in different application scenarios, can also be achieved with the same array architecture. The proposed CFRS decoder is implemented in a 3.3-V 0.35-μm CMOS technology with 2.2 × 2.2 mm2 core area and power dissipation of 13.3 and 1.23 mW in high- and low-speed decoding modes, respectively. View full abstract»

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  • A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

    Page(s): 663 - 668
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (485 KB) |  | HTML iconHTML  

    A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mVpp at 30 MHz. The OTA, fabricated in 0.5-μm CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a ±1.65-V power supply. View full abstract»

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  • A spread-spectrum clock generator with triangular modulation

    Page(s): 673 - 676
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB) |  | HTML iconHTML  

    In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. Only a divider and a programmable charge pump are added into a conventional clock generator to accomplish the spread-spectrum function. The proposed circuit has been fabricated in a 0.35-μm CMOS single-poly quadruple-metal process. The proposed SSCG can generate clocks of 66, 133, and 266 MHz with center spread ratios of 0.5%, 1%, 1.5%, 2%, and 2.5%. Experimental results confirm the theoretical analyses. View full abstract»

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  • High-sensitivity BiCMOS OEIC for optical storage systems

    Page(s): 579 - 584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (665 KB) |  | HTML iconHTML  

    A new BiCMOS optoelectronic integrated circuit (OEIC) for applications in advanced optical storage systems is presented. It is optimized with respect to high sensitivity and high speed. The photodiode and the amplifier are monolithically integrated on the same substrate in a commercial 0.8-μm BiCMOS process. Analytical expressions for the compensation capacitors and for the bandwidth of the OEIC are derived. Neglecting antireflection coating, no process modifications are necessary to produce the integrated photodiodes. A new offset compensation scheme is implemented in the amplifiers to allow for a small chip area and low power consumption. The OEIC shows a sensitivity of 43.3 mV/μW in combination with a -3-dB bandwidth of 60.2 MHz. View full abstract»

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  • A low-power precomputation-based fully parallel content-addressable memory

    Page(s): 654 - 662
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    This paper presents a novel VLSI architecture for a fully parallel precomputation-based content-addressable memory (PB-CAM) with low-power, low-cost, and low-voltage features. This design is based on a precomputation approach that saves not only power consumption of the CAM system, but also reduces transistor count and operating voltage of the CAM cell. In addition, the proposed PB-CAM word structure adopts the static pseudo-nMOS circuit design to improve system performance. The whole design was fabricated with the TSMC 0.35-μm single-poly quadruple-metal CMOS process. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with power consumption of 33 mW at 3.3-V supply voltage and works up to 30 MHz under 1.5-V supply voltage. View full abstract»

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  • A low-power ROM using charge recycling and charge sharing techniques

    Page(s): 641 - 653
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (867 KB) |  | HTML iconHTML  

    In a memory, most power is dissipated in high-capacitive lines such as predecoder lines, wordlines, and bitlines. To reduce the power dissipation in these high-capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. The first is the charge recycling predecoder (CRPD), the second is the charge recycling wordline decoder (CRWD), and the last one is the charge sharing bitline (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and wordlines. Theoretically, the power consumption in predecoder lines and wordlines are reduced to a half. The CSBL reduces the swing voltage in the ROM bitlines to very small voltage using a charge sharing technique with three small capacitors. The CSBL can significantly reduce the power dissipation in ROM bitlines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64%, respectively, of the power of previous ROM designs. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K × 16 bits was fabricated in a 0.35-μm CMOS process. The CRCS-ROM consumes 8.63 mW at 100 MHz with 3.3 V. The chip core area is 0.51 mm2. View full abstract»

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  • A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

    Page(s): 631 - 640
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (734 KB) |  | HTML iconHTML  

    To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-μm technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitor's series connection at pumping phase, while they are precharged in parallel. The hybrid folded current sense amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than ±2.5°C. View full abstract»

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  • An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter

    Page(s): 585 - 593
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    A tuning scheme for continuous-time high-Q biquad filters is presented. An improvement over the existing implementation of the modified-LMS Q-tuning scheme is proposed and efficiently combined with the frequency tuning based on phase-locked loops. The proposed scheme takes much less area without compromising the accuracy achieved previously. The proposed unified Q- and f0-tuning scheme does not require the Q-tuning loop to be slower than the f0-tuning loop. The optimal case is to have equal speeds for both loops. Also, a low-voltage pseudo-differential operational transconductance amplifier with inherent common-mode feedforward is introduced. The structure is fully symmetric and suitable for high-frequency applications. An experimental test chip is fabricated in standard CMOS 0.5-μm technology, with a bandpass filter of center frequency 100 MHz and Q of 20, along with the proposed tuning scheme. The measured Q-tuning error is around 1%. Expected and experimental results are in good agreement. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan