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Electron Device Letters, IEEE

Issue 1 • Date Jan. 2003

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Displaying Results 1 - 15 of 15
  • A novel InGaP/InGaAs/GaAs double /spl delta/-doped pHEMT with camel-like gate structure

    Publication Year: 2003 , Page(s): 1 - 3
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    The author reports a novel InGaP/InGaAs/GaAs double delta-doped pseudomorphic high-electron mobility transistor (pHEMT) with n/sup +/-GaAs/p/sup +/-InGaP/n-InGaP camel-like gate structure grown by MOCVD. Due to the p-n depletion from the p/sup +/-InGaP gate to the channel region and the presence of /spl Delta/Ec at the InGaP/InGaAs heterostructure, the turn-on voltage of gate is larger than 1.7 V. For a 1×100-μm2 device, the experimental results show an extrinsic transconductance of 107 mS/mm and a saturation current density of 850 mA/mm. Significantly, an extremely broad gate voltage swing larger than 6 V with above 80% maximum g/sub m/ is obtained. Furthermore, the unit current cut-off frequency fT and maximum oscillation frequency are up to 20 and 32 GHz, respectively. The excellent device performance provides a promise for linear and large signal amplifiers and high-frequency circuit applications. View full abstract»

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  • Explanation of anomalously high current gain observed in GaN based bipolar transistors

    Publication Year: 2003 , Page(s): 4 - 6
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB) |  | HTML iconHTML  

    The potential applications of GaN-based bipolar transistors have suffered a setback from poor ohmic contacts and leakage currents. We show in this work that the extrinsic current gain /spl beta//sub EXT/ measured at a low current level can be erroneously attributed to the gain of the intrinsic transistor. By accounting for leakage current coupled with poor ohmic contacts, we show that the observed very high /spl beta//sub EXT/ at low current levels can be modeled accurately. The real gain of the intrinsic transistor /spl beta//sub INT/ is generally much lower. As the current is increased, the effect of leakage currents is diminished, and /spl beta//sub EXT//spl rarr//spl beta//sub INT/. This model is satisfactorily applied to explain our experimental results. View full abstract»

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  • Innovative nitride passivated pseudomorphicGaAs HEMTs

    Publication Year: 2003 , Page(s): 7 - 9
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    A novel low-temperature nitride passivation technique using high-density inductively coupled plasma chemical vapor deposition (HD-ICP-CVD) with SiH4/N2 chemistries to passivate 0.15 μm pseudomorphic GaAs HEMTs has been developed for the first time. HD-ICP-CVD nitrides have higher density and lower hydrogen concentration than those of nitrides deposited by plasma-enhanced CVD (PECVD). Furthermore, HD-ICP-CVD passivated devices exhibit better performance in reverse breakdown voltage, transconductance, and cut-off frequency than those of PECVD passivated devices. The results achieved here warrant the applications of HD-ICP-CVD for next-generation nitride passivation in compound semiconductor technologies. View full abstract»

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  • A gate-charging model for ILD related plasma processes in MOSFETs

    Publication Year: 2003 , Page(s): 10 - 12
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    A model explaining gate-charging damage in MOSFETs observed during inter-layer-dielectric (ILD)-related plasma processes is reported. It indicates that the charging damage associated with the ILD plasma process can be related to the effect of photoconduction and/or capacitive impedance coupling of plasma potential through the multiple ILD layers. The model leads to a conclusion that by placing a larger-area lower-layer metal (such as Metal-1) plate or polysilicon plate at the gate terminal of MOSFETs, this ILD process-related charging damage can be eliminated or significantly reduced due to a substantial reduction in the gate-to-substrate impedance of the transistors. View full abstract»

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  • Improved hydrogen-sensitive properties of MISiC Schottky sensor with thin NO-grown oxynitride as gate insulator

    Publication Year: 2003 , Page(s): 13 - 15
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    Thin oxynitride grown in NO at low temperature was successfully used as gate insulator for fabricating MISiC Schottky hydrogen sensors. Response properties of the sensors were compared with other MISiC Schottky sensors with thicker or no oxynitride. It was found that the thin oxynitride played an important role in increasing device sensitivity and stability. Even at a low H/sub 2/ concentration, e.g., 100-ppm H/sub 2/ in N/sub 2/, a significant response was observed, indicating a promising application for detecting hydrogen leakage. Moreover, a rapid and stable dynamic response on the introduction and removal of H/sub 2//N/sub 2/ mixed gas was realized for the sensor. Improved interface properties and larger barrier height associated with the thin oxynitride are responsible for the excellent response characteristics. As a result, NO oxidation could be a superior process for preparing highly sensitive and highly reliable MISiC Schottky hydrogen sensors. View full abstract»

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  • Amorphous selenium photodetector driven by diamond cold cathode

    Publication Year: 2003 , Page(s): 16 - 18
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (335 KB) |  | HTML iconHTML  

    Amorphous selenium is one of the most promising candidates as photoconducting material for future imaging devices. It can exhibit ultra-high photosensitivity by using avalanche multiplication inside the solid. However, the requirement of high vacuum by the electron emitters prevents amorphous selenium from being a realistic imaging device in general. Diamond, with its outstanding properties of negative electron affinity and high chemical stability, can be an ultimate emitter with low extraction field and low vacuum operation, especially for imaging devices. This report presents the first successful operation of an amorphous selenium photodetector with low operational vacuum and extraction field using a diamond cold cathode. View full abstract»

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  • High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

    Publication Year: 2003 , Page(s): 19 - 21
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable "mother" substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm2/V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A/μm-channel-width at V/sub ds/=-0.1 V, sub-VT swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V. View full abstract»

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  • High-performance poly-Si TFTs made by Ni-mediated crystallization through low-shot laser annealing

    Publication Year: 2003 , Page(s): 22 - 24
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been fabricated using metal-induced crystallization followed by laser annealing (L-MIC). Laser annealing after MIC was found to yield a major improvement to the electrical characteristics of poly-Si TFTs. At a laser fluence of 330 mJ/cm2, the field effect mobility increased from 71 to 239 cm2/Vs, and the minimum leakage current reduced from around 3.0×10/sup -12/ A/μm to 2.9×10/sup -13/ A/μm at a drain voltage of 5 V. In addition, the dependence of the TFT characteristics on the laser energy density was much weaker than that for conventional excimer laser annealed poly-Si TFTs. View full abstract»

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  • Compensated back-channel TFTs in hydrogenated amorphous silicon

    Publication Year: 2003 , Page(s): 25 - 27
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (206 KB) |  | HTML iconHTML  

    Compensated back-channel inverted staggered TFTs have been made in a-Si:H. Donor impurities were implanted to form a good source and drain ohmic contact followed by an acceptor implant to compensate the channel region. TFTs have been made with no degradation of channel mobility due to the implants and a leakage current between source and drain comparable with the best TFTs made using conventional etched back-channel technology. View full abstract»

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  • Low RF noise and power loss for ion-implanted Si having an improved implantation process

    Publication Year: 2003 , Page(s): 28 - 30
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (222 KB) |  | HTML iconHTML  

    Very-low-transmission line noise of <0.25 dB at 18 GHz and low power loss /spl les/0.6 dB at 110 GHz have been measured on transmission lines fabricated on proton-implanted Si. In contrast, a standard Si substrate gave much higher noise of 2.5 dB and worse power loss of 5 dB. The good RF integrity of proton-implanted Si results from the high isolation impedance to ground, as analyzed by an equivalent circuit model. The proton implantation is also done after forming the transmission lines at a reduced implantation energy of /spl sim/4 MeV. This enables easier process integration into current VLSI technology. View full abstract»

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  • Low-frequency noise characteristics of ultrathin body p-MOSFETs with molybdenum gate

    Publication Year: 2003 , Page(s): 31 - 33
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    We report the low-frequency noise characteristics of ultrathin body (UTB) p-channel MOSFETs with molybdenum (Mo) as the gate material. Using the number fluctuation model with correlated mobility fluctuation, the dependence of the noise behavior on bias condition is explained. The impact of nitrogen implantation (for gate work function engineering) on the noise behavior is also presented. An exponential increase in noise with nitrogen implant dose is attributed to interface-trap generation caused by nitrogen penetration through the gate oxide. View full abstract»

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  • Mobility enhancement in surface channel SiGe PMOSFETs with HfO2 gate dielectrics

    Publication Year: 2003 , Page(s): 34 - 36
    Cited by:  Papers (12)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB)  

    We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si. View full abstract»

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  • RF capacitance-voltage characterization of MOSFETs with high leakage dielectrics

    Publication Year: 2003 , Page(s): 37 - 39
    Cited by:  Papers (29)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion. View full abstract»

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  • Thickness dependence of Weibull slopes of HfO2 gate dielectrics

    Publication Year: 2003 , Page(s): 40 - 42
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    Breakdown voltage distribution, Weibull slopes, and area scaling factors have been investigated for HfO/sub 2/ gate dielectrics in order to gain a better understanding of the breakdown mechanism. Weibull slope of thick HfO/sub 2/ (e.g., /spl beta//spl ap/4 for EOT=2.5 nm) is smaller than that of SiO/sub 2/ with similar physical thickness, whereas /spl beta/ of the thinner HfO/sub 2/ (e.g., /spl beta//spl ap/2 for EOT=1.4 nm) is similar to that of SiO/sub 2/. The implication of the thickness dependence of /spl beta/ is discussed. View full abstract»

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  • Improvement of short-channel characteristics of a 0.1-μm PMOSFET with ultralow-temperature nitride spacer by using a novel oxide capped boron uphill treatment

    Publication Year: 2003 , Page(s): 43 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    The thermal annealing at 720/spl deg/C for 2 hr (called boron uphill treatment) with an SiO2-capped layer was applied after source/drain extensions (SDE) implantation to improve the short channel characteristics of a 0.1-μm PMOSFET with an ultra-low temperature nitride spacer. The influence and the mechanism of the capped layer on this uphill treatment were investigated. The results show that the capped layer treatment indeed leads to a shallower junction, improved V/sub th/ roll-off characteristic, and added immunity against subsurface punchthrough. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee