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Electron Devices, IEEE Transactions on

Issue 1 • Date Jan. 2003

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Displaying Results 1 - 25 of 35
  • Foreword special issue on solid-state image sensors

    Publication Year: 2003 , Page(s): 1 - 3
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    Freely Available from IEEE
  • A CMOS image sensor with a double-junction active pixel

    Publication Year: 2003 , Page(s): 32 - 42
    Cited by:  Papers (6)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (794 KB)  

    A CMOS image sensor that employs a vertically integrated double-junction photodiode structure is presented. This allows color imaging with only two filters. The sensor uses a 184*154 (near-QCIF) 6-transistor pixel array at a 9.6-/spl mu/m pitch implemented in 0.35-/spl mu/m technology. Results of the device characterization are presented. The imaging performance of an integrated two-filter color sensor is also projected, using measurements and software processing of subsampled images from the monochrome sensor with two color filters. View full abstract»

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  • Excess noise and other important characteristics of low light level imaging using charge multiplying CCDs

    Publication Year: 2003 , Page(s): 239 - 245
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (578 KB)  

    This paper describes recent progress in technology of low light level image sensing using CCD sensors that multiply charge by impact ionization before its conversion into a voltage. The paper presents a brief description of the concept, the outline of a typical sensor design with some important details related to prevention of serial register blooming and achieving high dynamic range (DR), and then focuses primarily on the measurement and analysis of noise components that are important in these devices. The paper describes the theory of excess noise, shows the computation of the output signal probability distribution function (PDF), and the derivation of formula for the excess noise factor (ENF). Finally, it is concluded that under suitable conditions it is possible to achieve a single photon (electron) detection (SPD) performance. View full abstract»

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  • A 35-mm format 11 M pixel full-frame CCD for professional digital still imaging

    Publication Year: 2003 , Page(s): 254 - 265
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1459 KB) |  | HTML iconHTML  

    To meet the demand for higher resolution in professional digital imaging, an 11 M pixel, 35-mm format full-frame CCD image sensor was developed as an upgrade for an existing 6 M pixel CCD. This paper presents the device requirements, the architecture, modes of operation, and extensive evaluation results. View full abstract»

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  • An enhanced-performance CMOS imager with a flushed-reset photodiode pixel

    Publication Year: 2003 , Page(s): 48 - 56
    Cited by:  Papers (16)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (511 KB) |  | HTML iconHTML  

    A new front-end for photodiode-based CMOS imagers is presented. Degradation in imaging performance due to conventional hard- and soft-reset of pixels is analyzed. To overcome these limitations, the design and operation of a flushed-reset pixel is described. The flushed-reset pixel combines the best of hard- and soft-reset to simultaneously provide excellent radiometric accuracy, high linearity, no image lag, high saturation level, and reduced read-noise. The new front-end is implemented by changes to the column-circuitry only, leaving the pixel unchanged, preventing degradation of any unrelated imaging performance. It is compatible with large format imager implementation, has minimal impact on the frame-rate, and does not introduce any additional hot-carrier stress in the pixel. Data from a large format (5122) imager demonstrates the efficacy of the flushed-reset pixel approach. View full abstract»

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  • An image sensor with fast objects' position extraction function

    Publication Year: 2003 , Page(s): 184 - 190
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1086 KB) |  | HTML iconHTML  

    This paper describes a kind of vision chip, which is an integration of an image processing circuit with photoreceptors, that has a function of extracting objects' positions in focal plane. The objects' positions are output as their coordinates, which are useful for further detailed image recognition processing. The extraction processing has two steps; first, the flags indicating the objects' center positions are generated by analog parallel processing circuit implemented by resistive network and comparators, and next, the coordinates of such flags are generated by x- and y-priority encoders and a novel successive masking circuit. The designed circuit is capable of centroid detection for 23 × 23 pixels within 50 μs, and the processing time is expected not to increase so much even if the number of pixels increases, which will represent an improvement over the conventional processor-based image processing system. We also proposed and evaluated another implementation of a centroid detector using pulse-width adder. View full abstract»

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  • Total dose and displacement damage effects in a radiation-hardened CMOS APS

    Publication Year: 2003 , Page(s): 84 - 90
    Cited by:  Papers (28)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    A 512×512 CMOS active pixel sensor (APS) was designed and fabricated in a standard 0.5-μm technology. The radiation tolerance of the sensor has been evaluated with Co-60 and proton irradiation with proton energies ranging from 11.7 to 59 MeV. The most pronounced radiation effect is the increase of the dark current. However, the total ionizing dose-induced dark current increase is orders of magnitude smaller than in standard devices. It behaves logarithmically with dose and anneals at room temperature. The dark current increase due to proton displacement damage is explained in terms of the nonionizing energy loss of the protons. The fixed pattern noise does not increase with total ionizing dose. Responsivity changes are observed after Co-60 and proton irradiation, but a definitive cause has not yet been established. View full abstract»

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  • CMOS image sensor with NMOS-only global shutter and enhanced responsivity

    Publication Year: 2003 , Page(s): 57 - 62
    Cited by:  Papers (11)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (439 KB) |  | HTML iconHTML  

    Most CMOS image sensors today use the rolling shutter approach to control the integration time. This pixel architecture is advantageous where minimal pixel size is required to increase resolution or reduce over all chip size. For imaging of a fast moving object or when used with pulsed illumination, the rolling shutter approach is not suitable since it leads to severe distortion. Therefore, these applications require image sensors with a global shutter pixel architecture, which incorporates a sample-and-hold element in each pixel. Due to the optical exposure of the in-pixel storage element, shutter leakage is critical. First approaches which use separate wells in the pixel to isolate the storage node from the photodiode showed good shutter efficiency, but are bulky and led to large pixels with poor fill factor and bad responsivity. This paper presents an NMOS-only pixel with a global shutter and subthreshold operation of the NMOS sample-and-hold transistor to increase optical responsivity by a factor of five to 9 υV/photon, including fill factor. View full abstract»

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  • A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations

    Publication Year: 2003 , Page(s): 91 - 95
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB) |  | HTML iconHTML  

    An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-μm CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more than an order of magnitude. Through varying the bias conditions on the photogate, dynamic sensitivity can be obtained to increase maximum allowable illumination level. Combining the above two operation schemes, the dynamic range of this new cell can be extended by more than 20×. View full abstract»

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  • Transversal-readout architecture for CMOS active pixel image sensors

    Publication Year: 2003 , Page(s): 121 - 129
    Cited by:  Papers (3)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1133 KB) |  | HTML iconHTML  

    Novel architecture for CMOS active pixel image sensors (APSs), which eliminates the vertically striped fixed pattern noise (FPN), is presented. There are two kinds of FPN for CMOS APSs. One originates from the pixel-to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which results in a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and column-reset transistor, a source-follower input transistor, and a column-select transistor instead of the row-select transistor found in conventional CMOS APSs. The column-select transistor is connected to a signal line that runs horizontally instead of vertically. An experimentally fabricated 320×240-pixel CMOS APS employing the transversal-readout architecture exhibited neither vertically nor horizontally striped FPN. A buried-photodiode device with the transversal-readout architecture is also proposed. View full abstract»

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  • New signal readout method for ultrahigh-sensitivity CMOS image sensor

    Publication Year: 2003 , Page(s): 63 - 69
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (547 KB)  

    We propose a new signal readout method that uses a charge-transfer circuit. Its application is to an ultrahigh-sensitivity CMOS image sensor on which an avalanche-mode photoconductive film is overlaid. The charge-transfer circuit makes it possible to obtain high signal-to-noise ratio features by transferring signal charges accumulated in each photodiode to a parasitic capacitance that is small compared with the photodiode capacitance. A 138 × 138 passive-pixel prototype sensor that had the charge-transfer circuit in each column was fabricated and tested. The prototype's column-to-column fixed-pattern noise and random noise were, respectively, 56.7 and 58.4 dB below the saturation signal level, which demonstrated its potential as a signal readout circuit for a next-generation ultrahigh-sensitivity CMOS image sensor. View full abstract»

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  • Fully depleted, back-illuminated charge-coupled devices fabricated on high-resistivity silicon

    Publication Year: 2003 , Page(s): 225 - 238
    Cited by:  Papers (39)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (934 KB)  

    Charge-coupled devices (CCDs) have been fabricated on high-resistivity, n-type silicon. The resistivity, on the order of 10 000 Ω·cm, allows for depletion depths of several hundred micrometers. Fully depleted, back-illuminated operation is achieved by the application of a bias voltage to an ohmic contact on the wafer back side consisting of a thin in situ doped polycrystalline silicon layer capped by indium tin oxide and silicon dioxide. This thin contact allows for a good short-wavelength response, while the relatively large depleted thickness results in a good near-infrared response. View full abstract»

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  • A 9-V/Lux-s 5000-frames/s 512×512 CMOS sensor

    Publication Year: 2003 , Page(s): 136 - 143
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (690 KB) |  | HTML iconHTML  

    A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512×512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-μm 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering ∼1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted. View full abstract»

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  • An image sensor which captures 100 consecutive frames at 1000000 frames/s

    Publication Year: 2003 , Page(s): 144 - 151
    Cited by:  Papers (41)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1177 KB) |  | HTML iconHTML  

    An image sensor for a video camera of 1000000 frames per second (fps) was developed. The specifications of the developed sensor are as follows: 1) frame rate: 1000000 fps; 2) pixel count: 81 120 (=312×260) pixels; 3) total number of successive frames: 103 frames; 4) gray levels: 10 b; and 5) open area of each pixel (fill factor): 580 square micrometers (13%). The overwriting function is installed for synchronization of image capturing with occurrence of the target event. Sensitivity is significantly high with the large photogate. Some innovative technologies were introduced to achieve ultrahigh performance, including slanted linear CCD in situ storage, curving design procedure, and a CCD switch with fewer metal shunting wires. They are applicable to the development of other new high-performance image sensors. View full abstract»

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  • An APS with 2-D winner-take-all selection employing adaptive spatial filtering and false alarm reduction

    Publication Year: 2003 , Page(s): 159 - 165
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (610 KB)  

    An active pixel sensor (APS) with two-dimensional winner-take-all (WTA) detection is presented. This system-on-a-chip employs adaptive spatial filtering of the processed image, with bad pixel elimination and false alarm reduction in case of a missing object. The circuit has a unique ability of adaptive spatial filtering that allows removal of the background from the image, one stage before it is transferred to the WTA detection circuit. A test chip of a 64*64 array has been implemented in 0.5-μm CMOS technology, has a 49% fill factor, is operated by a 3.3-V supply, and dissipates 36 mW at video rate. System architecture and operation are discussed and measurements from the prototype chip are presented. View full abstract»

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  • Charge sharing modeling in pixel detectors with capacitive charge division

    Publication Year: 2003 , Page(s): 26 - 31
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB) |  | HTML iconHTML  

    Pixel detectors with junctions interleaved to readout nodes have been modeled as an electrical network. Time domain analysis of a signal induced by an ionizing particle has been performed. Results are reported, together with a comparison to experimental data. View full abstract»

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  • A 1.5-V 550-μW 176×144 autonomous CMOS active pixel image sensor

    Publication Year: 2003 , Page(s): 96 - 105
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1036 KB) |  | HTML iconHTML  

    This paper addresses the development of a micropower 176×144 CMOS active pixel image sensor that dissipates one to two orders of magnitude less power than current state-of-the-art CMOS image sensors. The chip operates from a 1.5-V voltage source and the power consumption measured for the chip running from an internal 25.2-MHz clock yielding 30 frames per second is about 550 μW. This amount enables the sensor to run from a watch battery. In order to achieve design goals, a low-power sensor design methodology is applied throughout the design process from system-level to process-level, while realizing the performance to satisfy the design specification. As an autonomous sensor, it can be operated with only three pads [GND, VDD (1.2-1.7 V), DATAOUT]. The die occupies 4 mm2 of silicon. View full abstract»

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  • A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

    Publication Year: 2003 , Page(s): 130 - 135
    Cited by:  Papers (23)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (527 KB)  

    This paper describes a large-format 4-Mpixel (2352×1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20×20 mm with a 7-μm pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization. View full abstract»

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  • Adaptive-integration-time image sensor with real-time reconstruction function

    Publication Year: 2003 , Page(s): 111 - 120
    Cited by:  Papers (17)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1292 KB) |  | HTML iconHTML  

    A computational image sensor is proposed in which the pixel controls its integration time to light intensity. The integration time of each pixel is selected from among several lengths of integration time and the integration time is shortened if the pixel intensity becomes saturated. Although the integration time of each pixel varies, the pixel intensity is adjusted on the sensor in real time. The dynamic range of the pixel value output from the proposed sensor is greatly widened. A prototype of 64×48 pixels has been fabricated by using 2-poly 2-metal 0.8-μm CMOS process. The proposed sensor has simple functions for the comparison of intermediate integration value and threshold to control the integration time and nonlinear image reconstruction. Because the maximum number of the comparison-reset operations during a frame is three, one of the four integration times can be selected pixel by pixel. The circuit and layout design of the prototype which has computational elements based on column parallel architecture are described and the fundamental functions have been verified. By the experiments, it has been verified that the sensor can achieve a wide dynamic range by adapting to light. View full abstract»

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  • A CMOS image sensor for high-speed active range finding using column-parallel time-domain ADC and position encoder

    Publication Year: 2003 , Page(s): 152 - 158
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1112 KB) |  | HTML iconHTML  

    In this paper, a smart image sensor for real-time and high-resolution three-dimensional (3-D) measurement to be used for sheet light projection is presented. It realizes not only a sufficiently high frame rate for real-time 3-D measurement, but also high pixel resolution due to a small pixel circuit and high subpixel accuracy due to gravity center calculation using an intensity profile. Simulation results show that the ultimate frame rate is 32.6 k frames/s (i.e., 31.8 range_map/s) in a 1024×1024 pixel sensor. A 3-b intensity profile allows subpixel accuracy under 0.1 pixel. The sensor using this architecture can acquire a two-dimensional (2-D) image as well, so a texture-mapped 3-D image can be reproduced by the same sensor. A 128×128 smart image sensor has been developed and successfully tested. A 2-D image, a range map, and a texture-mapped 3-D image have been acquired by the 3-D measurement system using the fabricated sensor. View full abstract»

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  • Ag-GaP Schottky photodiodes for UV sensors

    Publication Year: 2003 , Page(s): 215 - 217
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    We created UV-sensitive photodiodes based on a GaP Schottky barrier. A revised value of the Ag-GaP barrier height (1.55±0.03 eV) has been determined, and this value is much larger than commonly used for this system. Moreover, it depends on the parameters of the dielectric spacer and may be up to 1.7 eV. The high Schottky barrier improves the characteristics of photodetectors. We developed two types of such photodetectors. The first one is a selective UV photodiode with λmax=0.32 μm, Δλ=15 nm, and S=0.034 A/W based on the selective transparency of silver. The second one is a broad-band with λmax=0.42 μm, Δλ=230 nm, and S=0.19 A/W. View full abstract»

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  • Low-leakage-current and low-operating-voltage buried photodiode for a CMOS imager

    Publication Year: 2003 , Page(s): 43 - 47
    Cited by:  Papers (21)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (615 KB) |  | HTML iconHTML  

    A low-leakage current and low-operating-voltage buried-photodiode structure of CMOS image sensors has been developed. The new structure adopted a modified fabrication process as well as an additional shallow p+ layer structure that covers the entire surface of the deep n-type photodiode. The required operating voltage for complete charge transfer from the photodiode is 3.3 V. Furthermore, the leakage current level allows high-quality images comparable to those of CCD image sensors. View full abstract»

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  • CMOS imaging for automotive applications

    Publication Year: 2003 , Page(s): 173 - 183
    Cited by:  Papers (13)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1705 KB) |  | HTML iconHTML  

    This contribution is devoted to CMOS imaging for automotive applications. It is shown that unlike CCD-based imaging, imaging based on CMOS-sensing meets adequately requirements posed by automotive vision applications. In addition, besides classical vision, CMOS imaging enables new applications like, e.g., occupancy sensing, rangefinding, and 3-D vision. View full abstract»

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  • 3-D optical and electrical simulation for CMOS image sensors

    Publication Year: 2003 , Page(s): 19 - 25
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (646 KB)  

    The optical and electrical characteristics of CMOS image sensors, such as readout, saturation, reset, charge-voltage conversion, and crosstalk characteristics, are analyzed by a three-dimensional (3-D) device simulator SPECTRA and a 3-D optical simulator TOCCATA which were developed for the analysis of CCD image sensors. The model of readout operation for a buried photodiode with potential barrier and dip is discussed with consideration of thermal diffusion. The transient simulation is executed for readout and reset operation. A novel calculation method for photodiode saturation condition is proposed. The optical and electronic crosstalk is analyzed individually by ray-tracing and current calculation. It is found that the above methods successfully analyze the optical and electrical characteristics of CMOS image sensors. View full abstract»

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  • Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

    Publication Year: 2003 , Page(s): 106 - 110
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-μm and 0.25-μm CMOS with different pixels array sizes. For 2-μm SOI, results show a reduction by two of the power consumption and a dynamic range increase of 0.85 V under a 3-V supply. This results in an SNR of 79 dB instead of 76. Fixed pattern noise (FPN) is also reduced from 2.7 to 1.8 mV which represents 0.26% and 0.08% of the dynamic range, respectively. For 0.25-μm CMOS SOI, results show a reduction by 6.5 of the power consumption, FPN more than five time better, and a dynamic range increase of 0.29 V under a 1.5-V supply. However, because of the increase of the thermal noise due to the particular design choice, an SNR of 60.3 dB is achieved compared to 63 in bulk. A better SNR in SOI than in bulk can be achieved but at the expense of power consumption and FPN. However, this could be combined with an increase in pixels number in SOI compared to bulk. Potential results achievable in SOI have to our knowledge never been reached by bulk APS imagers up to now. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego