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IEE Proceedings - Computers and Digital Techniques

Issue 1 • Date 20 Jan. 2003

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Displaying Results 1 - 9 of 9
  • Optimal via minimisation by selection of layer assignment and routing ordering in a bubble-sorting-based non-Manhattan channel

    Publication Year: 2003, Page(s):21 - 27
    Cited by:  Papers (2)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (561 KB)

    It is well known that a non-Manhattan channel router never uses more tracks than a Manhattan router in a channel. For a bubble-sorting-based non-Manhattan channel, all the nets can be routed by k bubble-sorting swap passes in an optimal bubble-sorting solution, and these k swap passes can be further mapped onto k 1-track-routing processes in a two-layer routing model. However, these proposed bubbl... View full abstract»

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  • Efficient fault-tolerant scheme based on the RSA system

    Publication Year: 2003, Page(s):17 - 20
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (300 KB)

    Data security on the Internet is an area of considerable concern. A recently proposed fault-tolerant scheme for data encryption that was based on the RSA system is shown to be flawed. The flaw occurs if a malicious receiver keeps a sender's message and corresponding signature, then changes the message whilst retaining the existing signature. Under these circumstances the sender cannot deny having ... View full abstract»

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  • Efficient residue to binary converter

    Publication Year: 2003, Page(s):11 - 16
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (355 KB)

    Residue number system to binary number system conversion is a very basic operation in any interface between the two systems. A five-moduli set, in which each modulus has a specific form is presented. The moduli set is defined as (2k-2, 2k-1, 2k+1, 2k-2(k+1)2/+1, 2k+2(k+1)2/+1), where k is an odd positive integer. The mult... View full abstract»

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  • Two-dimensional DCT/IDCT architecture

    Publication Year: 2003, Page(s):2 - 10
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (558 KB)

    A fully parallel architecture for the computation of a two-dimensional (2D) discrete cosine transform (DCT), based on row-column decomposition is presented. It uses the same one-dimensional (1D) DCT unit for the row and column computations and (N2+N) registers to perform the transposition. It possesses features of regularity and modularity, and is thus well suited for VLSI implementatio... View full abstract»

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  • Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials

    Publication Year: 2003, Page(s):39 - 42
    Cited by:  Papers (13)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (306 KB)

    A bit-parallel systolic multiplier in the finite field GF(2m) over the polynomial basis, where irreducible trinomials xm+xn+1 generate the fields GF(2m) is presented. The latency of the proposed multiplier requires only 2m-1 clock cycles. The architecture has the advantage of low latency, low circuit complexity and high throughput, as compared with tradi... View full abstract»

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  • Analysis of new pivoting strategy for the LDLT decomposition on a multiprocessor system with distributed memory

    Publication Year: 2003, Page(s):53 - 63
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (611 KB)

    It is well known that optimal control techniques can provide the ability to design suitable strategies, however, the on-line computing requirements are excessive. The normal procedure is to make various assumptions so that the processing demands are reduced. Based on these assumptions, sequences of linear-quadratic-performance optimal control problems need to be considered. These in turn give rise... View full abstract»

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  • Editorial

    Publication Year: 2003, Page(s): 1
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (188 KB)

    First Page of the Article
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  • Fault-tolerant wormhole routing in torus networks with overlapped block faults

    Publication Year: 2003, Page(s):29 - 37
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (732 KB)

    A fault-tolerant routing algorithm for torus networks that uses only three virtual channels is presented. The proposed algorithm is based on the block fault model, which is suitable for modelling faults at the board level in networks with grid structures. Messages are routed via shortest paths when there are no faults. However, if a message is blocked by a faulty block, the message will use a deto... View full abstract»

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  • Efficient hardware architecture for fast IP address lookup

    Publication Year: 2003, Page(s):43 - 52
    Cited by:  Papers (12)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (638 KB)

    A multi-gigabit Internet protocol (IP) router may receive several million packets per second from each input link. For each packet, the router needs to find the longest matching prefix in the forwarding table in order to determine the packet's next-hop. An efficient hardware solution for the IP address lookup problem is presented. The problem is modelled as a searching problem on a binary-trie. Th... View full abstract»

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