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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Issue 11 • Date Nov 2002

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  • High-speed ΣΔ modulators with reduced timing jitter sensitivity

    Publication Year: 2002, Page(s):712 - 720
    Cited by:  Papers (37)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (522 KB) | HTML iconHTML

    As higher and higher frequency signals are sampled, clock jitter limits the achievable signal-to-noise ratio (SNR) in an analog-to-digital converter (ADC). This clock jitter limit is reviewed for upfront sampled ADCs and continuous-time (CT) sigma-delta modulators (ΣΔMs). A pulse-shaped feedback digital-to-analog converter (DAC) is proposed to mitigate the jitter-imposed SNR limit in C... View full abstract»

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  • On the design and implementation of FIR and IIR digital filters with variable frequency characteristics

    Publication Year: 2002, Page(s):689 - 703
    Cited by:  Papers (52)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2451 KB) | HTML iconHTML

    This paper studies the design and implementation of finite-impulse response (FIR) and infinite-impulse response (IIR) variable digital filters (VDFs), whose frequency characteristics can be controlled continuously by some control or tuning parameters. A least squares (LS) approach is proposed for the design of FIR VDFs by expressing the impulse response of the filter as a linear combination of bas... View full abstract»

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  • PLL-based frequency discriminator using the loop filter as an estimator

    Publication Year: 2002, Page(s):721 - 727
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    In this paper we present a new phase-locked-loop-based frequency discriminator architecture that performs both A/D conversion and frequency demodulation. In addition, the loop filter is designed as a linear estimator. Two forms of linear estimators are investigated. Simulation results show that for a minimum shift key signal at 400 MHz IF, the proposed frequency discriminator achieves an SNR impro... View full abstract»

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  • A new SC differentiator for two-path bandpass ΔΣ modulator design

    Publication Year: 2002, Page(s):728 - 732
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (337 KB) | HTML iconHTML

    A new architecture of a fully differential switched capacitor (SC) differentiator is proposed as the building block of two-path bandpass SC ΔΣ modulators. Compared to other SC differentiators, the pole in its transfer function is not sensitive to capacitor mismatches, and there is less switch thermal noise in the new architecture. The opamp in the differentiator has a smaller capacitan... View full abstract»

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  • Analysis of jitter in phase-locked loops

    Publication Year: 2002, Page(s):704 - 711
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (501 KB) | HTML iconHTML

    Jitter in clock signals is analyzed, linking noise in free-running oscillators to short-term and long-term time-domain behavior of phase-locked loops. Particular attention is given to comparing the impact of 1/f noise and white noise in oscillators and frequency dividers on jitter in phase-locked loops of first- and second-order. Theoretical analysis is supported by results obtained using mixed-si... View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

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