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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 4 • Date Oct. 2002

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Displaying Results 1 - 17 of 17
  • Foreword - Fifth international IEEE symposium on high density packaging and component failure analysis (HDP'02)

    Page(s): 251 - 252
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    Freely Available from IEEE
  • Author index

    Page(s): 370 - 372
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    Freely Available from IEEE
  • Subject index

    Page(s): 372 - 379
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    Freely Available from IEEE
  • Encapsulation process development for flexible-circuit based chip scale packages

    Page(s): 344 - 354
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3039 KB) |  | HTML iconHTML  

    The ultimate driving forces for the development of small form-factor chip scale packages (CSPs) are the market demands for small, light and high performance products. The flex-based μBGA technology has been a very successful package format, and tremendous efforts have been implemented in the process development for the technology. In this article, three flex-based chip scale packages (based on patented μBGA technology) will be discussed. The focus will be on the encapsulation process development. Because of the unique package structures and material sets used in the flex-based CSPs, various encapsulation challenges were raised. The encapsulation solutions are compared and discussed for each type of flex-based μBGA technologies, including the dispensing pump technologies, material characterization, process characterization and optimization. Based on the evaluation results, type C μBGA technology is recommended for its simple assemble process flow, balanced protection on beam leads and solder ball joints and shorter manufacturing cycle time as well. View full abstract»

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  • Process development and adhesion behavior of electroless copper on liquid crystal polymer (LCP) for electronic packaging application

    Page(s): 273 - 278
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1091 KB) |  | HTML iconHTML  

    Liquid crystal polymer (LCP) has potentially a very wide application as substrate material in electronic packaging applications because of its unique advantages. The work in this paper was performed to realize the metallization of LCP for the purpose of board fabrication, and to study the adhesion between deposited copper and LCP. A homogenous electroless plated copper layer on LCP with 4 to 5 μm thickness was achieved, while it increased up to 40 μm with the subsequent electroplating. The timescale of etching, deposit ion rate, and pH value were gradually changing during the plating process and the influences on copper layer quality were investigated. The adhesion force of the copper-LCP layer system was measured by a shear-off-method. Scanning electron microscopy (SEM) was used to check the surface morphology after etching and the interface after shearing on both the backside of the copper layer and the LCP side. The relationship between the shear-off adhesion of copper and the time of chemical etching before plating was examined, and the optimal etching time is discussed. Heat treatment after plating was used, and it was shown that this significantly improved the adhesion strength. View full abstract»

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  • A computational study on solder bump geometry, normal, restoring, and fillet forces during solder reflow in the presence of liquefied underfill

    Page(s): 308 - 317
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1023 KB) |  | HTML iconHTML  

    A computational survey was performed to evaluate the effect of volume and material properties on a concurrent underfilling and solder reflow manufacturing technique applied to flip-chip technology. Fillet geometry in addition to collapsed solder ball geometry and forces during solder reflow in the presence of liquefied underfill are reported. Targeted material properties included surface tension, wetting angles, and process parameters such as underfill volume. A regression model is presented representing over 1000 case studies completed using surface evolver. Also, a multiple ball model was developed to study the solder ball array behavior. Modeling results are presented. Application of this model for wafer applied coating underfill thickness prediction was also studied including the fillet forces added to a multiple-ball-model. Behavior and force studies combining all these effects were performed and are presented. Finally, a more realistic arrangement consisting of circular and square solder pad geometries combined is modeled for a single ball. The models results are expanded to include a multiball model employing a commonly used regression method. Solder joints were cross-sectioned and measured after reflow in the presence of a fluxing underfill for comparison to model predictions. The experimental results agree within 1.5%. View full abstract»

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  • Solder parameter sensitivity for CSP life-time prediction using simulation-based optimization method

    Page(s): 318 - 325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (777 KB) |  | HTML iconHTML  

    Finite element modeling (FEM) is widely used for estimating the solder joint reliability of electronic packages. However, the solder properties are strongly process and geometry dependent. Even for the same type of solder, measurements conducted by different people at different locations show different results, due to differences in application conditions, benching etc. Those differences may lead to differences in constitutive equations and/or the parameter values. Therefore the effect of the solder parameter variation and parameter sensitivity should be taken into account before a reliable solder fatigue prediction can be made. In this research, a simulation based optimization method is used to investigate the sensitivity of the chosen solder parameters for the solder fatigue prediction using an inelastic strain criterion. View full abstract»

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  • Development of lead-free wave soldering process

    Page(s): 289 - 299
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2020 KB) |  | HTML iconHTML  

    Lead-free wave soldering was studied in this work using a 95.5Sn/3.8Ag/0.7Cu alloy. A process DOE was developed, with three variables (solder bath temperature, conveyor speed, and soldering atmosphere), using a dual wave system. Four no-clean flux systems, including alcohol- and water-based types, were included in the evaluation. A specially designed "Lead-Free Solder Test Vehicle", which has various types of components, was used in the experiments. Both organic solderability preservative (OSP) and electroless nickel/immersion gold (Ni/Au, or ENIG) surface finishes were studied. Soldering performance (bridging, wetting and hole filling) was used as the responses for the DOE. In addition, dross formation was measured at different solder bath temperatures and atmospheres. Dross formation with Sn/Ag/Cu bath was compared to that with eutectic Sn/Pb bath. Regarding the connector-type component, a pad design giving the best soldering performance was evaluated based on the DOE results. Finally, a confirmation run with the optimum flux and process parameters was carried out using the Sn/Ag/Cu solder, and a comparative run was made with the Sn/Pb solder alloy and a no-clean flux used in production. The soldering results between the two runs indicate that with optimum flux and process parameters, it is possible to achieve acceptable process performance with the Sn/Ag/Cu alloy. View full abstract»

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  • Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?

    Page(s): 262 - 272
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (755 KB) |  | HTML iconHTML  

    Advances in integrated circuits and packaging technologies provided us more implementation options for mixed-signal systems. Emerging technologies are represented by system-on-chip (SoC) and system-on-package (SoP). In order to make a design decision for optimal system implementation, it is hence becoming more and more important to address the cost and performance issues for various implementation options early in a system deign phase. In this paper, we develop a modeling technique for a priori cost and performance estimations for mixed-signal system implementations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitry parts, using special substrate materials (e.g., silicon-on-insulator), and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or "virtual components," yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, are considered. Finally, an efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints. Case studies for SoC and SoP integration are performed using COMSI. View full abstract»

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  • A new bumping process using lead-free solder paste

    Page(s): 253 - 256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB) |  | HTML iconHTML  

    In this paper, we report development of a new process for lead-free solder bumping with no flux residues, using stencil printing and hydrogen radicals, which can lessen both the environmental load and the manufacturing cost of solder bumping. In this process the reduction of the hydrogen radicals, instead of the flux, will eliminate the surface oxides of the stencil printed lead-free solder paste. Sn-3.0Ag-0.5Cu lead-free solder paste, which contains no residue flux was printed on an 8-in wafer. Hydrogen plasma was radiated for a minute during the reflow process, and the printed paste formed a bump. Reflow experiments without hydrogen radicals treatment were also carried out for comparison, where no successful reflow could be observed. View full abstract»

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  • Electrode sticking during micro-resistance welding of thin metal sheets

    Page(s): 355 - 361
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1510 KB) |  | HTML iconHTML  

    The electrode sticking mechanism and factors affecting the sticking, including welding current, weld time, electrode tip coating, electrode force and electrode spacing, were studied during micro-resistance welding of very thin nickel-plated steel to nickel sheets in the assembly of a cell-phone battery package. The results indicated that electrode sticking was caused by local metallurgical bonding between the electrode and the nickel-plated steel sheet. The sticking force was proportional to the total area of the local bonds and to the bonding strength between the electrode and sheet. Reducing welding current and weld time, and increasing electrode force and electrode spacing were found to reduce electrode sticking. Welding electrodes with tips coated with TiC metal matrix composite were tried as an alternative to the regular CuCrZr electrode and were found to be more resistant to sticking. View full abstract»

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  • An investigation on thermal reliability of underfilled PBGA solder joints

    Page(s): 284 - 288
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    The failure mechanism, as well as cycles to failure, of two groups of PBGA samples (with/without underfill) for thermal shock in the range of -40□-125□ were presented. The experiment shows that the solder ball in the samples without underfill cracked after 500 times cycle, while no crack was found in the underfilled samples even after 2700 cycles. However, the die attach layer delaminated after 500 cycles and the PCB cracked in the underfilled samples after long time cycling. C-SAM is employed to investigate the delamination in the underfilled samples. Highly concentrated stress-strain induced by the CTE mismatch between the BGA component and the PCB, coarsened grain and two kinds of intermetallic compounds (Ni3Sn2/NiSn4) which formed during reflow and thermal cycling and their impact on the reliability of solder joints are discussed in this paper. The initiation of the crack and its propagation are also presented in this paper. By means of dye penetrant test, the authors reveal the distribution of microcracks in the solder ball array. In addition, this paper includes results of simulation, which further verified its conclusions. View full abstract»

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  • The absorption ink transfer mechanism of gravure offset printing for electronic circuitry

    Page(s): 335 - 343
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (711 KB) |  | HTML iconHTML  

    The gravure offset method has been developed toward an industrially viable printing technique for electronic circuitry. In order to obtain the optimum ink resin for printing lines of required thickness (>5 μm) of narrow lines (down to 25 μm), several ink resin systems have been assessed in previous studies by the authors. The best printed results were obtained with a novel ink using a hydrocarbon resin. This ink did not comply with the traditional ink transfer mechanism based on evaporation of the solvent, but with a postulated new "absorption mechanism.". View full abstract»

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  • Thermal and mechanical stability of soldering QFP with Sn-Bi-Ag lead-free alloy

    Page(s): 257 - 261
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (779 KB) |  | HTML iconHTML  

    Thermal stability of the circuit boards with a quad flat package (QFP) soldered with Sn-58wt%Bi-(0, 0.5 and 1.0) wt% Ag and their microstructural features were evaluated. The addition of 1.0 wt% Ag causes the formation of large primary Ag3Sn precipitates in the solder while no primary Ag3Sn is found in Sn-57Bi-0.5Ag. Thermo-Calc calculation indicates that the lowest limit content for the formation of primary Ag3Sn is about 0.8 wt%. Heat-exposure below 100°C has no serious degradation on the joint structure for all solders. Heat-exposure at 125°C caused serious degradation in joint strength for all alloys. The contamination of Pb from Sn-Pb surface plating on the components reduces the interface tolerance by forming ternary Sn-Pb-Bi phase melting at low temperature. Thermal fatigue between -20 and 80°C does not have any significant influence on joint structure. View full abstract»

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  • Pressure-assisted low-temperature sintering of silver paste as an alternative die-attach solution to solder reflow

    Page(s): 279 - 283
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    Pressure-assisted low-temperature sintering of silver paste is shown to be a viable alternative to solder reflow as a die-attachment solution. A quasihydrostatic pressure is used to lower the sintering temperature. The effect of parameters such as temperature and pressure are investigated. Characterization of the silver-attached samples shows a significant improvement in electrical conductivity, thermal conductivity and mechanical strength of the joint. Given that silver deforms with little accumulation of inelastic strains, and given the absence of large voids in the attachment layer, it is also expected that the joint to be more resistant to fatigue failure than a solder attached junction. Due to the high melting temperature of silver, this alternative process is also suitable for high temperature packages. View full abstract»

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  • An integrated process modeling methodology and module for sequential multilayered substrate fabrication using a coupled cure-thermal-stress analysis approach

    Page(s): 326 - 334
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (950 KB) |  | HTML iconHTML  

    An integrated process modeling methodology using a coupled cure-thermal-stress analysis approach has been developed to determine the evolution of warpage and stresses during the sequential fabrication of high-density electronic packaging structures. The process modeling methodology has been demonstrated, for example, with a bi-layer structure consisting of a 3 mil (76.2 μm) thick Vialux 81 photo-definable dry film (PDDF) polymer on a silicon substrate. Extensive material characterization of the thermo-mechanical properties of the thin film polymer is presented, including the development of a viscoelastic material model. The predicted warpage values have been validated with shadow Moire experiments, while the predicted stress values have been validated with experimental data using the Flexus Thin Film Stress Measurement Apparatus. Good agreement is seen between the predicted and the experimental warpage and stress values during the entire cure cycle. Finally, the importance of incorporating viscoelastic polymer behavior and processing history is emphasized in the context of developing the multi-layered high-density wiring integrated substrate fabrication process. View full abstract»

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  • Characterization of lead-free solders and under bump metallurgies for flip-chip package

    Page(s): 300 - 307
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    A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55°C/+150°C air-to-air thermal cycling condition. View full abstract»

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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University