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Circuits, Devices and Systems, IEE Proceedings -

Issue 56 • Date Oct/Dec 2002

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Displaying Results 1 - 13 of 13
  • CMOS low power baseband chain for a GSM/DECT multistandard receiver

    Page(s): 337 - 347
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1104 KB)  

    A CMOS low power baseband chain for an GSM/DECT multistandard receiver is presented. The chain uses a low power class AB digitally controlled filter and variable gain amplifier blocks to provide a low power, DSP controllable design solution. The chain and the building blocks are fabricated using standard N-well CMOS technology. Measurement results indicate that the chain can operate in GSM or DECT mode with a total standby current consumption less than 1.5 mA, while providing a gain control range from -6 dB to 23 dB in 1 dB steps. The chain achieves an input referred noise less than 31 nV/√(Hz) and an out-of-band IIP3 of more than 30 dBm. View full abstract»

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  • 1 mW CMOS polyphase channel filter for Bluetooth

    Page(s): 348 - 354
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (599 KB)  

    A polyphase transconductor-capacitor (Gm-C) channel filter for a low-IF Bluetooth transceiver is described. It is designed in a 2.5 V, 0.25 μm standard CMOS process and employs a novel fully differential transconductor. Simulated performance is presented showing good fifth-order bandpass filter response (1 MHz centre frequency, 1.2 MHz bandwidth), 1 dB compression at 1.3 V pk-pk, signal-to-noise ratio of 68.2 dB and an input third-order intermodulation product of 34.2 dBV. The power consumption is 1 mW and estimated chip area is 0.1 mm2. View full abstract»

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  • Very low-voltage (0.8V) CMOS receiver frontend for 5 GHz RF applications

    Page(s): 355 - 362
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1002 KB)  

    A fully integrated low-voltage RF receiver front end for 5 GHz radio applications, implemented in a standard 0.18 μm CMOS technology, is presented. The receiver consists of a differential low noise amplifier, an active mixer, and a quadrature voltage-controlled oscillator. The complete receiver is packaged in a standard 24-pin ceramic flat pack and consumes 56 mW from a 0.8 V supply. Measurement results show that the receiver has an overall noise figure of 7 dB, a -1 dBm input-referred IIP3, and 22 dB of image rejection. A stand-alone single-ended version of the LNA is also presented. Simple mechanisms for tuning the gain and the centre frequency of the LNA are proposed. With a supply voltage of 1 V, the LNA provides a power gain of 13.2 dB, has a noise figure of 2.5 dB, and over 10 dB of gain control and 360 MHz of frequency tuning. The LNA still operates well from a supply voltage as low as 0.7 V, providing a power gain of 7 dB. View full abstract»

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  • Analytical modelling for the RESURF effect in JI and SOI power devices

    Page(s): 273 - 284
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1179 KB)  

    The authors present a review and assessment of state-of-the-art analytical models which describe the breakdown behaviour of JI and SOI RESURF power devices. The results are compared with numerical values, and a short evaluation of strengths and weaknesses specific to each model is given. A new modelling concept for the breakdown regime in RESURF power structures is introduced, and the results are assessed against numerical values. The same technique can be used to derive the breakdown voltage of RESURF devices fabricated in JI and SOI technologies, and is potentially useful for non-standard technologies, such as linearly graded SOI, partial SOI and 3-D RESURF. The model provides accurate description for punch-through, non-punch-through and volume breakdown. View full abstract»

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  • 2 GHz controllable power amplifier in standard CMOS process for short-range wireless applications

    Page(s): 363 - 368
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (685 KB)  

    The authors present the design and implementation of a broadband radiofrequency power amplifier in a standard CMOS technology for short-range wireless applications. The amplifier is implemented in a standard 0.35 μm triple metal CMOS process. The amplifier is capable of delivering a maximum output power of 16.6 dBm at 1.91 GHz, and of 16 dBm at 2 GHz using a 3.3 V supply with an overall measured power added efficiency (PAE) of 33%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. The level of output power can be controlled in 2 dB steps using a number of parallel semi-cascode stages. View full abstract»

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  • Non-complex signal processing in a low-IF receiver for GSM

    Page(s): 322 - 330
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (948 KB)  

    The low-IF receiver architecture has already proved its effectiveness in mobile radio applications such as GSM. By using an IF of half the channel spacing to facilitate the removal of DC offsets, it achieves the sensitivity of a conventional superhet whilst offering the full integration potential of a direct-conversion receiver. Previous attempts to improve its multi-mode capability have focussed on digitising as much as possible of the IF signal chain with the help of a complex ADC. The channel filtering then moves into the digital domain where reprogramming is comparatively easy for operation in other modes. However, the combination of an increased dynamic range requirement and the need for a complex ADC can make the circuit design problem unduly difficult. In the receiver architecture to be described, the need for a complex ADC is avoided by processing only the real part of the low-IF signal. This substantially simplifies the ADC design whilst retaining all the advantages of a digitised, low-IF receiver. Simplification of the ADC design is the main objective but there is also scope for a 17% reduction in power consumption. View full abstract»

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  • High-performance low-power current sense amplifier using a cross-coupled current-mirror configuration

    Page(s): 308 - 314
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (989 KB)  

    A high-performance current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Simulation results have shown that the new sense amplifier gives performance leverage over the conventional sense amplifier circuits in terms of speed and power. View full abstract»

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  • Parasitic-aware design and optimisation of RF power amplifiers

    Page(s): 369 - 375
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (671 KB)  

    Design considerations using parasitic-aware synthesis and optimisation techniques are presented for a three-stage 30 dBm 900 MHz class-E power amplifier implemented in a 0.35 μm standard digital CMOS process. Using both bond wire and on-chip square spiral inductors, the PA achieves 49% drain efficiency η and 25 dB power gain using a single 3.3 V power supply. Experience shows that the class-E PA design space is complex with many local minima. Thus, simulated annealing optimisation is chosen because of its inherent hill climbing ability that allows it to avoid being trapped in sub-optimum local minima. The paper first demonstrates the severe effects or parasitics by comparing results of switching power amplifier designs with both parasitic-free and parasitic-laden on-chip inductors. The results of parasitic-aware synthesis are then presented, including an illustration of its potential for power amplifier topology selection. View full abstract»

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  • Efficient path-delay fault simulation for standard scan design

    Page(s): 315 - 320
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (609 KB)  

    In spite of using scan designs, there remain problems concerning the generation and confirmation or test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm. View full abstract»

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  • Continuous time quadrature band-pass ΔΣ modulator with input mixers

    Page(s): 331 - 336
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (899 KB)  

    A continuous time quadrature band-pass ΔΣ modulator preceded by input mixers is presented. Complex band-pass ΔΣ modulators provide better performance than band-pass ΔΣ modulators in digitising complex signals due to more efficient noise shaping (Yantzi et al., 1997). Continuous time implementation of the second-order ΔΣ noise shaping loop filter is preferred to a switched capacitor structure (van der Zwan and Dijkmans, 1996). Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be down-converted to a digital I and Q output stream at a clock rate of 128 MHz. It is designed as a front-end for a low power receiver with a 2 MHz IF bandwidth centred around 4 MHz and attains a signal-to-noise ratio higher than 60 dB. The ΔΣ ADC and mixer are integrated in a 0.25 μm CMOS technology and consume 14 mW from a 2 V supply. View full abstract»

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  • Algorithm for building a neural network for function approximation

    Page(s): 301 - 307
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (597 KB)  

    A technique for constructing a multilayer tree-structured neural network, which provides a continuous, piece-wise linear function approximation, is presented. The method uses a growth network with linear threshold neurons. Neurons are added to a binary tree until the approximation error at all sampling points is brought down to within a specified ±Δ. The number of neurons in the constructed network depends on the samples provided as well as the specified tolerance Δ, thus enabling a trade-off between accuracy and network size. In comparison to approaches such as back propagation, the proposed technique requires no assumptions regarding the number of neurons, learning rate, momentum term, or initial weight values. It also does not suffer from problems of local minima. Examples are presented to illustrate the effectiveness of the technique. View full abstract»

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  • Design for optimum classical filters

    Page(s): 291 - 300
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (948 KB)  

    Filter optimisation is the improvement of one or more characteristics of a filter. Such improvement is beneficial to the design in some sense. The work request focuses on the magnitude response of classical filters that are polynomial approximations to the ideal 'brick-wall' filter. Given a set of passband and stopband frequency requirements, optimisation then becomes the achievement of any combination of the following criteria while maintaining filter order fixed: maximisation of the band-edge selectivity; minimisation of the passband ripple; maximisation of the stopband attenuation. Such optimisation results in new pole/zero locations that implement the above features without increasing filter complexity. A graphical technique for specifying optimum filters in the above sense is presented exploiting the special capability of filter nomographs. Tradeoffs in the criteria above are related to critical pole-pair Q and filter delay responses. A design example is presented to illustrate the power and ease of designing classical filters with optimum magnitude responses. View full abstract»

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  • Characterisation of substrate noise in FLASH A/D converters

    Page(s): 285 - 290
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (706 KB)  

    A method for modelling electromagnetically coupled substrate noise in mixed signal integrated circuits was developed. This method was then used to characterise the substrate noise issues in FLASH analogue to digital (A/D) converters. The model was also used to study the addition of the P+ guards around the input devices of the comparators in order to assess their effectiveness in reducing the substrate noise. Finally, the effect of variations in the package's bond wire inductances in the net injected current noise was modelled. View full abstract»

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