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Circuits and Systems Magazine, IEEE

Issue 4 • Date 2002

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Displaying Results 1 - 7 of 7
  • VLSI transactions best paper award

    Publication Year: 2002 , Page(s): 49
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    Freely Available from IEEE
  • IEEE CAS fellow profiles 2002: Michael W. Marcellin - For contributions to data compression and constrained coding systems

    Publication Year: 2002 , Page(s): 52
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    Freely Available from IEEE
  • IEEE CAS fellow profiles 2002: Jan Van der Spiegel - For contributions in biologically motivated sensors and information processing systems

    Publication Year: 2002 , Page(s): 52
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    Freely Available from IEEE
  • IEEE CAS fellow profiles 2002: Wolfgang Porod - For contributions to circuit concepts and architectures for nanoelectronics

    Publication Year: 2002 , Page(s): 52
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    Freely Available from IEEE
  • Implementation approaches for the Advanced Encryption Standard algorithm

    Publication Year: 2002 , Page(s): 24 - 46
    Cited by:  Papers (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    This paper addresses various approaches for efficient hardware implementation of the Advanced Encryption Standard algorithm. The optimization methods can be divided into two classes: architectural optimization and algorithmic optimization. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased by processing multiple rounds simultaneously at the cost of increased area. Architectural optimization is not an effective solution infeed-back mode. Loop unrolling is the only architecture that can achieve a slight speedup with significantly increased area. In non-feedback mode, subpipelining can achieve maximum speedup and the best speed/area ratio. Algorithmic optimization exploits algorithmic strength inside each round unit. Various methods to reduce the critical path and area of each round unit are presented. Resource sharing issues between encryptor and decryptor are also discussed. They become important issues when both encryptor and decryptor need to be implemented in a small area. View full abstract»

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  • A framework for reconfigurable computing: task scheduling and context management-a summary

    Publication Year: 2002 , Page(s): 48 - 51
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    Reconfigurable computing is consolidating itself as a real alternative to ASICs (Application Specific Integrated Circuits) and general-purpose processors. The main advantage of reconfigurable computing derives from its unique combination of broad applicability, provided by the reconfiguration capability, and achievable performance, through the potential parallelism exploitation. The key aspects of the scheduling problem in a reconfigurable architecture are discussed, focusing on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations. View full abstract»

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  • Technology trends toward a system-in-a-module in power electronics

    Publication Year: 2002 , Page(s): 4 - 22
    Cited by:  Papers (49)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    Currently, assemblies of power semiconductor switches and their associated drive circuitry are available in modules. From a few 100 watts downward, one finds silicon monolithic technology as the integration vehicle, while upward into the multi-kilowatt range, mixed mode module construction is used. This incorporates monolithic, hybrid, surface mount and wirebond technology. However, a close examination of the applications in motor drives and power supplies indicates that there has been no dramatic volume reduction of the subsystem. The power semiconductor modules have shrunk the power switching part of the converter, but the bulk of the subsystem volume still comprises the associated control, sensing, electromagnetic power passives and interconnect structures. The paper addresses the improvement of power processing technology through advanced integration of power electronics. The goal of a subsystem in a module necessitates this advanced integration. The central philosophy of this technology development research is to advance the state of the art by providing the concept of integrated power electronics modules (IPEMs). The technology underpinning such an IPEM approach is discussed. The fundamental functions in electronic power processing, the materials, processes and integration approaches and future concepts are explained. View full abstract»

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Aims & Scope

Insofar as the technical articles presented in the proposed magazine, the plan is to cover the subject areas represented by the Society's transactions, including: analog, passive, switch capacitor, and digital filters; electronic circuits, networks, graph theory, and RF communication circuits; system theory; discrete, IC, and VLSI circuit design; multidimensional circuits and systems; large-scale systems and power networks; nonlinear circuits and systems, wavelets, filter banks, and applications; neural networks; and signal processing.

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Meet Our Editors

Editor-in-Chief
Chi K. Tse
Hong Kong Polytechnic University