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Computers and Digital Techniques, IEE Proceedings -

Issue 6 • Date Nov 2002

 This issue contains several parts.Go to:  Part Supplement 

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Displaying Results 1 - 4 of 4
  • Earle latch design for high performance pipeline

    Publication Year: 2002 , Page(s): 245 - 248
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (351 KB)  

    A modified Earle latch, that requires only one copy of the input data instead of the two copies required in the original Earle scheme is presented. In SPICE simulations, the modified Earle latch has the smallest area and lowest power dissipation compared to other static latches. Chip implementation shows that the speed of an adder using the proposed latch outputs can be improved from 33 MHz to 60 MHz compared to the speeds obtainable using the original Earle latch. View full abstract»

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  • Method of time Petri net analysis for analysis of fault trees with time dependencies

    Publication Year: 2002 , Page(s): 257 - 271
    Cited by:  Papers (6)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (820 KB)  

    In order to make computer-aided control systems as safe as possible, a number of analysis techniques have been developed. One of these is fault tree analysis. A fault tree (FT) represents causal and generalisation relations between events (e.g. a hazard and its causes). However, it can express neither time relations between events nor detection and protection times. Time Petri nets (TPNs) can model all the above aspects. Thus, TPNs can be used for analysing and verifying time-dependent fault trees (FTs). One of the limitations of classical TPN analysis is the large number of TPN states. Even for a small FT this number can turn out to be vast. The authors introduce a new method for analysing such TPNs that model FTs. We do not consider all states that are reachable from the initial marking in classical TPN analysis but only those that lead to the occurrence of a hazard. Such an approach simplifies the procedure and results in cleaner final conclusions. If the hazard is reachable there is a need for safety measures to be taken. FT analysis and modelling of protection using TPNs will be illustrated using an example. View full abstract»

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  • Self-diagnostic tools of the APEmille parallel machine

    Publication Year: 2002 , Page(s): 273 - 279
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (554 KB)  

    The authors describe the self-diagnostic tools of the APEmille SIMD machine, whose logical architecture is a three-dimensional torus of processors. The tools are aimed at implementing system-level diagnosis using a comparison model. The diagnostic model accounts for some critical features of the APEmille architecture, and has been validated by means of VHDL simulation. Essentially, diagnostic tools force all processors to synchronously execute the same test program using the same data set, and compare the outputs of adjacent processors in real time. The diagnostic tools also implement a preliminary test session aimed at covering faults that might disrupt the comparison model. The diagnosis algorithm and the test programs used in comparison tests are also described. View full abstract»

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  • Technology mapping algorithm for heterogeneous field programmable gate arrays

    Publication Year: 2002 , Page(s): 249 - 255
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (482 KB)  

    To maximise device utilisation, a heterogeneous field programmable gate array (FPGA) provides either an array of homogeneous lookup tables (LUTs) of different sizes or an array of physically heterogeneous LUTs. It is shown that heterogeneous FPGAs have a significant number of desirable attributes. A technology mapping algorithm is proposed for heterogeneous FPGAs. The technology mapping problem is first formulated as a flow network problem. Then, an algorithm based on the min-cost max-flow algorithm is presented to select a proper set of feasible LUTs for various objectives. Two objectives: (i) the minimum number of LUTs; and (ii) the total area composed of LUTs and routing area are discussed. The algorithm is tested on the MCNC benchmark circuits and produces better characteristics than existing LUT based FPGA mapping algorithms. View full abstract»

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