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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 5 • Date May 1991

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Displaying Results 1 - 13 of 13
  • A new circuit optimization technique for high performance CMOS circuits

    Publication Year: 1991 , Page(s): 670 - 677
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    A novel transistor sizing technique with a concise problem formulation and rigorous optimization scheme is described. A circuit optimization technique for high-performance CMOS circuits is presented for proper balance of chip speed and area. The timing specification is accommodated as a design constraint, and reliability issues in the charge sharing and noise margin, which have been neglected in previous optimization tools, are also embedded into the design constraints. The optimization scheme used in this approach does not require derivatives, and therefore, can be used for a broad class of continuous cost functions. Special attention is given to the most effective use of silicon area based on the sensitivity of the delay time with respect to the transistor size. Excessively large transistor sizes are avoided by using the resource redistribution scheme. This timing allocation scheme allows the computation time to be linearly proportional to the number of gates View full abstract»

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  • Fault simulation of unconventional faults in CMOS circuits

    Publication Year: 1991 , Page(s): 677 - 682
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    The authors present a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate-level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for transistor stuck-open and stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. The following general conclusions are drawn from these results: (1) shorts between transistor gate and drain are adequately detected by stuck-at oriented test patterns, and, hence, they do not represent a significant problem in IC testing: (2) the coverage of transistors stuck-open is significantly dependent on the test pattern generation method used; (3) the detectability of bridgings depends strongly on the circuit topology; and (4) the indirect coverage of transistors stuck-on is inadequate, essentially because a large number of them are undetectable View full abstract»

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  • Global flow optimization in automatic logic design

    Publication Year: 1991 , Page(s): 557 - 564
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    A method for optimizing digital logic networks is described. This approach uses the techniques of global flow analysis to efficiently gather information about the relationship between different wires in a circuit and uses methods from network flow to use this information to optimize the circuit. It differs from earlier methods for optimization of multilevel logic networks in that valid rearrangements of signal connections depend on the maintenance of global circuit invariants. An algorithm which reduces the problem of finding small circuits in this equivalence class to the problem of finding a min-cut in an associated graph is described. This algorithm has been implemented and forms part of an automatic design system in use within IBM. The authors describe the results of experiments undertaken to evaluate the effect of the techniques View full abstract»

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  • Test generation and verification for highly sequential circuits

    Publication Year: 1991 , Page(s): 652 - 667
    Cited by:  Papers (72)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1504 KB)  

    A novel test procedure that exploits the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit is presented. Initially, before test generation, separate sum-of-product representations of the complete or partial ON-sets and OFF-sets of each of the flip-flop inputs and primary outputs of the sequential circuit are extracted using the PODEM algorithm. Fast algorithms for state justification and state differentiation based on this representation are described. The algorithm developed for test generation is extended to verification of finite-state machines (FSMs). The algorithm for state differentiation based on the ON- and OFF-set representation is modified for verification purposes. The authors present experimental results that illustrate the superior performance of this approach as compared to previous approaches to FSM verification. They are able to verify examples with significantly more memory elements than previous approaches View full abstract»

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  • A recursive technique for computing delays in series-parallel MOS transistor circuits

    Publication Year: 1991 , Page(s): 589 - 595
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    An efficient recursive technique for computing the Elmore delay in series-parallel resistance-capacitance (RC) networks is presented. The time complexity of the algorithm is on the order of the number of resistors times the number of nodes to which the delay has to be computed. In this respect it is superior to other known methods, particularly to that of P.K. Chan Karplus. Although that algorithm is more general, the present method should be attractive given the fact that many VLSI MOS circuits are based on design styles which are restricted to series-parallel transistor networks, which, in particular, exclude bridges. A special type of series-parallel RC circuit occurs in interconnection networks driven by multiple sources. A variation on the first algorithm, which is especially useful in a hierarchical simulator, is presented for computing the Elmore delay in such networks View full abstract»

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  • Parallel algorithms for VLSI circuit extraction

    Publication Year: 1991 , Page(s): 604 - 618
    Cited by:  Papers (11)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1324 KB)  

    The authors propose parallel algorithms to speedup the VLSI circuit extraction task. Given a VLSI layout as input, the problem of circuit extraction consists of determining the circuit connectivity and estimating the various electrical parameters such as the resistances of lines, capacitances of nodes, and dimensions of devices. Circuit extraction is a computationally intensive problem. The basic approach used in the parallel algorithms is the partitioning of a circuit into small regions, assigning each region to a processor and having the processors cooperate in performing the extraction procedures. The authors present a number of partitioning strategies that could be used. The authors have implemented the parallel algorithms on an Intel iPSC2 hypercube and an Encore 510 multimax shared memory multiprocessor View full abstract»

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  • A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis

    Publication Year: 1991 , Page(s): 629 - 642
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    An analytic charge-conserving non-quasi-static (NQS) model is derived for long-channel MOSFETs and has been implemented in SPICE3. The model is based on approximate solutions to the transient current continuity equation, an analytic equations are derived for node charges using the charge-sheet formulation. The NQS effects in several test circuits, which include a pass transistor, a CMOS inverter chain, and a differential sample-hold circuit, are stimulated. Excellent agreements have been observed among this work, PISCES (2-D device simulation), the 1-D numerical simulation, the multiple lump model, and CODECS (a mixed device and circuit simulation). However, large differences have been observed between this work and conventional quasi-static (QS) models. The model computation time of this work implemented in SPICE3 is about 2-3 times larger than those of QS models (BSIM, Level-2 Meyer) in SPICE3 View full abstract»

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  • An accurate analytical delay model for BiCMOS driver circuits

    Publication Year: 1991 , Page(s): 577 - 588
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (956 KB)  

    An analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by using a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses to account for significant differences between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the driver delay time is also investigated. The model has been applied to find an optimal area allocation between the CMOS and bipolar parts of the driver circuit when the total available area is limited as in the standard cell configuration View full abstract»

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  • Analog functional simulator for multilevel systems

    Publication Year: 1991 , Page(s): 565 - 576
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB)  

    The authors describe a high-level functional analog simulator for hybrid logic/analog networks. it forms one level of an experimental multilevel simulation system which is currently under development. The functional simulator is described in detail, and the structure of the multilevel simulator is briefly outlined. It can be used as a stand-alone system but was developed specifically for coupling with other levels of simulation which also use time responses (or voltage waveforms). Since Boolean algebra cannot operate with time responses, a new algebra is developed. It eliminates the unknown state, the main obstacle in coupling analog simulation to logic simulation. Logic states are replaced by operations on time functions, in this case represented by piecewise linear segments. High-level analog operations are also possible. The simulator based on these ideas was used to solve several high-level analog problems. The examples presented demonstrate its application View full abstract»

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  • Improving the computational efficiency of the tree relaxation method for an iterative solution of linear circuit equations

    Publication Year: 1991 , Page(s): 668 - 670
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    The problem of improving the computational efficiency of a method for an iterative solution of a linear circuit equation, known as the tree relaxation (TR) method, is investigated. It is shown that the adoption of the tree-branch voltages instead of the node voltages, resulting in a tree relaxation modified (TR) method, represents a more advantageous choice for the network variables. The extra processing needed for setting up the fundamental cut-set matrix allows a significant reduction of the computational burdens to be obtained. These savings are even more substantial if a transient analysis is to be performed. It is shown that the choice of the tree-branch voltages yields further advantages if a parallel version of the TRM is to be implemented View full abstract»

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  • Two-dimensional process simulation using verified phenomenological models

    Publication Year: 1991 , Page(s): 643 - 651
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    Two-dimensional (2-D) effects are becoming increasingly important in the diffusion of impurities in submicrometer silicon devices. The authors describe a 2-D process simulator, PREDICT2, that handles implant damage effects, annealing, and lateral diffusion. PREDICT2 simulates the diffusion of impurities in silicon by using phenomenological diffusion coefficients. The phenomenological models are verified by comparing simulated and experimental results. This approach is compared with that of point-defect-based simulators. The experimental technique for measuring impurity profiles in two dimensions is outlined. The method for generating diffusion models is illustrated by examining 2-D phosphorous diffusion. Numerical simulations and experimental measurements are compared. The numerical methods used in the simulator are described, and directions for future work are suggested View full abstract»

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  • A framework for industrial layout generators

    Publication Year: 1991 , Page(s): 596 - 603
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    The MACLOG family of layout generators creates parameterized custom layouts for many of the cells in the AT&T Cell Library. The authors describe not the MACLOG generators themselves, but the MACLOG framework that is the base of all the generators. The MACLOG generators are built on an object-oriented framework. Though object-oriented design techniques have been described in the literature, the MACLOG framework is one of the first such frameworks used to build an industrial-quality layout generator set. The attempt to build an object-oriented framework structure around the module types results in excessive code duplication and a hard-to-maintain structure. The authors found the service hierarchy-the types of information provided to the user by the generator-often to be a more effective axis for decomposition of functions in the framework. The authors describe the MACLOG framework and detail experiments with framework structure View full abstract»

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  • SMART-II: a three-dimensional CAD model for submicrometer MOSFET's

    Publication Year: 1991 , Page(s): 619 - 628
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (780 KB)  

    The authors describe a three-dimensional CAD model for submicrometer MOSFETs. The model has been implemented in a three-dimensional process/device integrated simulator, SMART-II, using a supercomputer. The MOS device model for hot electron transport is based on a modified current relation including an electron temperature effect in an inhomogeneous field. The need for an improved mobility model in an inversion layer and an impact ionization model using the recent experimental data for the mean free path is discussed with emphasis on the numerical simulation for I/V characteristics of small-geometry MOSFETs from the threshold regime to the avalanche regime. It is found that this approach is effective in realizing a three-dimensional CAD model for 0.5-μm MOSFETs. An application of the model reveals a three-dimensional effect of avalanche breakdown behavior in small-geometry MOSFETs View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu