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Solid-State Circuits, IEEE Journal of

Issue 1 • Date Jan. 2003

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Displaying Results 1 - 24 of 24
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  • An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator

    Page(s): 71 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (821 KB) |  | HTML iconHTML  

    Explores the MOS interface-trap charge-pump as an ultralow constant-current generator for analog CMOS applications. Charge pumping techniques in general are more suitable than conventional continuous-time techniques for ultralow current generation because the linear controllability of current by frequency is maintained regardless of the level of current. An interface-trap pump has the same property but the minimum charge it puts out per cycle is at least two orders of magnitude smaller than that of a switched-capacitor charge pump. This helps generate the same current more accurately at a much higher frequency with a much smaller filter capacitance. The paper presents a simplified model of the terminal characteristics of the interface-trap pump and an evaluation of its performance as a stand-alone current generator. Cascoding and complementary pumping are introduced as measures of performance improvement. Temperature sensitivity, pulse feedthrough, controllability, matching, reliability, and trimming issues are addressed. Transconductor circuits built with the charge pump are presented and experimentally evaluated. View full abstract»

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  • Sub-1-V CMOS proportional-to-absolute temperature references

    Page(s): 84 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (525 KB) |  | HTML iconHTML  

    Presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (μA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-μW integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-μm very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+>60 dB. Hence, the resulting PTAT circuits are suitable for very-low-voltage system-on-a-chip applications in digital CMOS technologies. View full abstract»

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  • A remark on carry-free binary multiplication

    Page(s): 159 - 160
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    It is shown that any binary multiplier needs some mechanism for carry propagation. As a consequence, the carry-free multiplier presented in the paper by Kim et al. (see IEEE J. Solid-State Circuits, vol. 36, p. 1538-1544, Oct. 2001) cannot work correctly. To demonstrate that fact, implementation-independent test patterns are constructed. View full abstract»

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  • A new successive approximation architecture for low-power low-cost CMOS A/D converter

    Page(s): 54 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (575 KB) |  | HTML iconHTML  

    A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm2 with the TSMC 0.35-μm single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs. View full abstract»

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  • A 1.76-GHz 22.6-mW ΔΣ fractional-n frequency synthesizer

    Page(s): 138 - 140
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    A ΔΣ fractional-N frequency synthesizer for the 2-GHz-range wireless communication applications is implemented in a 0.35-μm BiCMOS process, using only CMOS components. The synthesizer achieves a close-in phase noise of -81 dBc/Hz, while the spurious tones are at -85 dBc. The synthesizer features a multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation. The entire prescaler, including the gigahertz-speed first stages, is implemented using full-swing logic. The current source structure employed in the charge pump provides a constant output current over a wide, almost rail-to-rail output voltage range. The power dissipation of the synthesizer chip is 22.6 mW from a 2.7-V supply. View full abstract»

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  • A 3-V, 0.35-μm CMOS Bluetooth receiver IC

    Page(s): 30 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (791 KB) |  | HTML iconHTML  

    A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm2 die using TSMC 0.35-μm standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply. View full abstract»

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  • A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

    Page(s): 13 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-μm CMOS technology in an area of 1.75×1.55 mm2, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10-9 with a pseudorandom bit sequence of 223-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply. View full abstract»

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  • A low-voltage low-power voltage reference based on subthreshold MOSFETs

    Page(s): 151 - 154
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-μm CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm/°C in the range -25 to +125°C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported. View full abstract»

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  • Single-ended to differential converter for multiple-stage single-ended ring oscillators

    Page(s): 141 - 145
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB) |  | HTML iconHTML  

    This paper presents an improved technique for single-ended to differential conversion that allows for the use of single-ended CMOS ring oscillators in an otherwise fully differential integrated circuit environment. An interpolating resistor network is used to derive a fully differential representation of the single-ended voltage-controlled-oscillator (VCO) signal. The technique preserves the fundamental noise performance of single-ended ring oscillators in the presence of supply and substrate interference. Experimental results in a 0.35-μm CMOS process show the applicability of this technique at the VCO speeds of up to 1.3 GHz. View full abstract»

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  • A 113-dB DSD audio ADC using a density-modulated dithering scheme

    Page(s): 114 - 119
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (347 KB) |  | HTML iconHTML  

    A stereo audio delta-sigma A/D converter is implemented to support both the standard pulse-code modulation audio and the direct stream digital (DSD) output format. It provides all the standard audio rates up to 192 kHz. A sixth-order, single-bit modulator is employed to achieve the noise performance as well as the bitstream output required by the DSD format. A novel density-modulated dithering scheme is utilized to dramatically reduce the tone level in the signal band without compromising the stability of the high-order modulator. This analog-to-digital converter achieves a dynamic range of 113 dB and a total harmonic distortion +N of 105 dB. It is fabricated in a 0.35-μm CMOS process with a die size of 10.5 mm2. View full abstract»

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  • A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

    Page(s): 107 - 113
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (489 KB)  

    A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-μm CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s. View full abstract»

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  • DC-coupled IF stage design for a 900-MHz ISM receiver

    Page(s): 126 - 134
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (582 KB) |  | HTML iconHTML  

    This paper presents a DC-coupled 900-MHz ISM band RF front-end for a short-range wireless receiver. The front-end, fabricated in a 0.5-μm CMOS process, is intended as a test vehicle to verify the proposed DC-coupled topology. In this topology, a low-frequency feedback circuit suppresses the DC offset and low-frequency noise at the mixer output. The DC-coupled topology is compared with traditional AC coupling. We show that there is a tradeoff between bandwidth and midband loss in a fully integrated AC-coupled system. The proposed DC-coupling technique does not impose this tradeoff. The DC-coupled topology was verified via simulation and measurements from the test vehicle. View full abstract»

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  • Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

    Page(s): 43 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (949 KB)  

    This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers and a DC-offset cancellation scheme. The direct conversion scheme combined with a multiphase sampling fractional-N prescaler alleviates the problems of the direct conversion transmitter and receiver. Digital gain control is merged into the baseband filters and variable-gain amplifiers to optimize the linearity of the system, reduce the noise, and improve the sensitivity. Variable-gain amplifiers with DC-offset cancellation loop eliminate the DC-offset in each stage. The chip implemented in 0.35-μm CMOS technology shows the experimental results of 6 dBm maximum output power with 38-dB adjacent channel power rejection ratio at 1.92 MHz, 50-dB dynamic range, and 363-mW power consumption in the transmitter. The receiver shows -115.4 dBm sensitivity, a 4.0-dB noise figure, and a dynamic range of 80-dB with 396-mW power consumption. View full abstract»

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  • Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier

    Page(s): 22 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (507 KB) |  | HTML iconHTML  

    The design of two highly efficient line drivers in a digital 0.35-μm, 3.3-V technology are presented. The self-oscillating power amplifier (SOPA) architecture has been developed in order to obtain a high efficiency for systems with a high crest factor like discrete multitone modulated xDSL modems. The SOPA architecture is an unclocked switching-type line driver. By using self-oscillation and noise-shaping, a high signal linearity can be obtained for low over-switching ratios. By coupling two SOPA line drivers with a signal transformer, the two limit cycle oscillations are pulled toward synchronization. This gives an important mean switching frequency suppression toward the line. The need for an extra filter dealing with the mean switching frequency is in that way heavily relaxed. A zeroth-order SOPA and a third-order SOPA are prototyped. The zeroth-order line driver meets ADSL-Lite specifications with a missing tone power ratio (MTPR) of 41 dB for an 800-kHz bandwidth. The maximum efficiency is 41%. The third-order version meets ADSL and VDSL specifications with an MTPR of 56 dB and an 8.6-MHz bandwidth. An efficiency of 47% was measured for an ADSL signal with a crest factor >5. View full abstract»

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  • A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme

    Page(s): 155 - 158
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (451 KB) |  | HTML iconHTML  

    A 256×144-bit TCAM is designed in 0.18-μm CMOS. The proposed TCAM cell uses 4T static storage for increased density. The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs. The scheme achieves a match-time of 3 ns and operates at a minimum supply voltage of 1.2 V. View full abstract»

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  • High-gain SiGe transimpedance amplifier array for a 12×10 Gb/s parallel optical-fiber link

    Page(s): 4 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (923 KB) |  | HTML iconHTML  

    A transimpedance amplifier array for 12 parallel optical-fiber channels each operating at 10 Gb/s is presented, which is used in the receiver of short-distance links. It stands out for the following features: high gain (transimpedance 25 kΩ in the limiting mode), high input sensitivity and wide input dynamic range (input current swing from 20 to 240 μAp-p), constant output voltage swing (differential 0.5 Vp-p at 50 Ω load), and low power consumption (1.4 W) at a single supply voltage (5 V). Each channel has its own offset-current control circuit. To the best of the authors' knowledge, the total throughput of 12×10 Gb/s=120 Gb/s is the highest value reported for a single-chip amplifier array. The target specifications have been achieved with the first technological run without needing any redesign. This fact demonstrates that the inherent severe crosstalk problems of such high-gain amplifier arrays can reliably be solved by applying adequate decoupling measures and simulation tools. View full abstract»

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  • A CMOS voltage reference based on weighted ΔVGS for CMOS low-dropout linear regulators

    Page(s): 146 - 150
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (895 KB) |  | HTML iconHTML  

    A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-μm CMOS technology (Vthn≈|Vthp|≈0.9 V at 0°C). The occupied chip area is 0.055 mm2. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 μA. A typical mean uncalibrated temperature coefficient of 36.9 ppm/°C is achieved, and the typical mean line regulation is ±0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV/√(Hz) and that at 100 kHz is 1.6 nV/√(Hz). View full abstract»

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  • A practical micropower programmable bandpass filter for use in bionic ears

    Page(s): 63 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (734 KB) |  | HTML iconHTML  

    Subthreshold Gm-C filters offer the low power and wide tunable range required for use in fully implantable bionic ears. The major design challenge that must be met is increasing the linear range. A capacitive-attenuation technique is presented and refined to allow the construction of wide-linear-range bandpass filters with greater than 1 Vpp swings. For a 100-200 Hz fully differential filter with second-order roll off slopes and greater than 60 dB dynamic range, experimental results from a 1.5-μm, 2.8-V BiCMOS chip yield only 0.23 μW power consumption; for a 5-10 kHz filter with the same specifications the power only increased to 6.36 μW. Fully differential filters with first-order slopes had a dynamic range of 66 dB and power consumptions of 0.12 and 3.36 μW in the 100-200 Hz and 5-10 kHz cases, respectively. We show that our experimental results of noise and linear range are in good accord with theoretical estimates of these quantities. View full abstract»

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  • Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode

    Page(s): 89 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB)  

    An integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1-μH off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5-μm CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters. View full abstract»

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  • A signal-processing CMOS image sensor using a simple analog operation

    Page(s): 101 - 106
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    We have developed a high-density CMOS image sensor with a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel size and real-time operation are achieved by using a four-transistor and one-capacitor pixel scheme and column-parallel on-chip analog operation. The chip includes 512 (H) ×384 (V) effective pixels. Each pixel has a sufficient fill factor of 24% in an area of 9.3×9.3 μm2. The dynamic range at the wide dynamic-range mode is a maximum 97 dB against 51 dB at the normal-readout mode. The chip consumes 79 mW, and the gain-control amplifier and 8-b analog-to-digital converter operate at 46 frames/s using a 3.3-V single power supply. View full abstract»

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  • An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering

    Page(s): 120 - 125
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    A compact, high-resolution analog-to-digital converter (ADC) especially for sensors is presented. The basic structure is a completely digital circuit including a ring-delay-line with delay units (DUs), along with a frequency counter, latch, and encoder. The operating principles are: (1) the delay time of the DU is modulated by the analog-to-digital (A/D) conversion voltage and (2) the delay pulse passes through a number of DUs within a sampling (= integration) time and the number of DUs through which the delay pulse passes is output as conversion data. Compact size and high resolution were realized with an ADC having a circuit area of 0.45 mm2 (0.8-μm CMOS) and a resolution of 12 μV (10 kS/s). Its nonlinearity is ±0.1% FS per 200-mV span (1.8-2.0 V), for 14-b resolution. Sample holds are unnecessary and a low-pass filter function removes high-frequency noise simultaneously with A/D conversion. Thus, the combination of this ADC and a digital filter that follows can eliminate an analog prefilter to prevent the aliasing before A/D conversion. Also, both this ADC can be shrunk and operated at low voltages, so it is an ideal means to lower the cost and power consumption. Drift errors can be easily compensated for by digital processing. View full abstract»

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  • A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology

    Page(s): 135 - 137
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB) |  | HTML iconHTML  

    This paper presents a 28-GHz monolithic quadrature voltage-controlled oscillator (QVCO) realized in a preproduction 0.4-μm SiGe bipolar technology with 85-GHz transit frequency. QVCOs efficiently drive quadrature modulators and demodulators in receivers or transmitters. At 28.9 GHz, the circuit provides -14.7 dBm of output power and phase noise of -84.2 dBc/Hz at a 1-MHz offset. The two output signals are in quadrature with phase error of about 5°. Tuning of the QVCO may be done in the frequency range from 24.8 to 28.9 GHz with nearly constant output power. The circuit consumes 25.8 mA from the 5 V voltage supply. View full abstract»

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  • Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm"

    Page(s): 160 - 161
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (217 KB)  

    For original paper see ibid., vol. 36, no. 10, p. 1538-1545 (Oct. 2001). In the aforementioned paper by Kim et al., a multiplier is presented which produces the result in radix-2 signed-digit representation. It is claimed that this representation can be converted into conventional magnitude representation by an algorithm which has no carry propagation. To the commenters this algorithm seems incorrect. The critical situation is a string which consists of a sequence of zeros followed by a -1; in such a case a carry is needed and the algorithm proposed is deemed incorrect. Consequently, it is pointed out that the proposed algorithm produces a correct multiplication result in conventional magnitude representation only if the signed-digit string does not have a sequence of 0's followed by a -1. The commenters show a multiplication example using the proposed conversion algorithm in which this situation occurs. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan