IEEE Journal on Selected Areas in Communications

Issue 1 • January 1986

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Displaying Results 1 - 24 of 24
  • [Front cover and table of contents]

    Publication Year: 1986, Page(s): 0
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    Freely Available from IEEE
  • [Back cover]

    Publication Year: 1986, Page(s): 0
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    Freely Available from IEEE
  • Guest Editorial

    Publication Year: 1986, Page(s):1 - 3
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    Freely Available from IEEE
  • Design and VLSI Implementation of a Concurrent Solver for N-Coupled Least-Squares Fitting Problems

    Publication Year: 1986, Page(s):39 - 48
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    Most algorithms for high,quality modeling and coding of stochastic sequences (speech or images) make extensive use of matrix operations. Because of the high computational complexity of these operations, the use of conventional implementation techniques and architecture designs would almost certainly rule out such algorithms as candidates for real-time signal processing. In this paper, we present a... View full abstract»

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  • A Fast VLSI Multiplier for GF(2m)

    Publication Year: 1986, Page(s):62 - 66
    Cited by:  Papers (50)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (405 KB)

    Multiplication in the finite fieldGF(2^{m}) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication inGF(2^{m}), which isO(m)in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given.... View full abstract»

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  • VLSI Structures for Viterbi Receivers: Part I--General Theory and Applications

    Publication Year: 1986, Page(s):142 - 154
    Cited by:  Papers (44)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1257 KB)

    A taxonomy of VLSI grid model layouts is presented for the implementation of certain types of digital communication receivers based on the Viterbi algorithm. We deal principally with networks of many simple processors connected to perform the Viterbi algorithm in a highly parallel way. Two interconnection patterns of interest are the "shuffleexchange" and the "cube-connected cycles." The results a... View full abstract»

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  • Implementation of a Viterbi Processor for a Digital Communications System with a Time-Dispersive Channel

    Publication Year: 1986, Page(s):160 - 167
    Cited by:  Papers (13)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1034 KB)

    This paper describes the theory, design, and testing of a Viterbi processor for a digital communication system with intersymbol interference over fading time-dispersive channels. The requirement is to implement the Viterbi algorithm for a channel memory of 9 baud at a data rate of 2400 bits/s. The processor is partitioned into three subprocessors corresponding to the correlation, state metric eval... View full abstract»

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  • A Line Termination Circuit for Burst-Mode Digital Subscriber Loop Transmission

    Publication Year: 1986, Page(s):176 - 183
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (713 KB)

    This paper describes a line termination circuit for burst-mode bidirectional digital subscriber loop transmission. It incorporates the most advanced LSI technology to obtain compactness, low cost, and high reliability. Two CMOS LSI's have been developed; one is a line termination LSI (LT) and another is a circuit termination LSI (CT). LT LSI adopts a novelRCactive filter-type equalizer ... View full abstract»

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  • Fast Error Decoding with Binary VLSI Logic

    Publication Year: 1986, Page(s):168 - 175
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    Maximal distance binary codes that are composed of individual characters from the residues of pairwise prime polynomials are constructed and compared to Reed-Solomon codes. Although these binary residue codes are not as efficient as R-S codes in that codeword lengths are shorter, error decoding involves only binary and not finite field operations and thus allows faster decoding and greater data ra... View full abstract»

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  • A Versatile Spectrum Modification Technique

    Publication Year: 1986, Page(s):100 - 111
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    The spectrum modification technique is a digital procedure for placing the spectrum of any band-limited signal-analog or digital within an arbitrarily chosen set of (nonoverlapping) frequency intervals, the sum of whose lengths is not less than the original bandwidth of the signal. Because it can serve the function of several digital techniques, such as mixing, interpolating, and decimating, and c... View full abstract»

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  • Implementation of a 32 Kbit/s ADPCM Codec Using a General-Purpose Digital Signal Processor

    Publication Year: 1986, Page(s):125 - 132
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    This paper describes an implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764). A single-channel ADPCM codec is realized by two FDSP-3 chips-one for the encoder and the other for the decoder. Meticulous programming techniques are employed to achieve exact computation of the CCITT algorithm exploiting all the available resou... View full abstract»

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  • High-Speed Si-Bipolar and GaAs Technologies

    Publication Year: 1986, Page(s):24 - 31
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    Improvements in the design and fabrication of the basic transistor devices and improvements in circuit layout and design techniques have dramatically increased the performance of high-speed bipolar integrated circuits. Refinement of standard processes like lithography and the introduction of new processes such as low-pressure epitaxy and dry-etching techniques have largely contributed to the advan... View full abstract»

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  • Application of a VLSI Vector Quantization Processor to Real-Time Speech Coding

    Publication Year: 1986, Page(s):112 - 124
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1720 KB)

    The major obstacle which has limited the use of Vector Quantization (VQ) for real-time speech coding is the computationally demanding codebook-search algorithm. The essential task of this algorithm, pattern matching, has several properties which make it amenable to VLSI realization using a highly concurrent processor architecture. A VLSI pattern-matching chip provides the essential building-block ... View full abstract»

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  • RNS Digital Filtering Structures for Wafer-Scale Integration

    Publication Year: 1986, Page(s):67 - 80
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1352 KB)

    Wafer-scale integration (WSI) compresses a large amount of microelectronics representing a complete digital system onto a single intact wafer. This approach is desirable for applications requiring extensive computational capabilities but only limited input and output connections. Its primary advantage is an improvement in total system density. However, such designs must have built-in fault toleran... View full abstract»

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  • Design Examples of System Partitioning and Performance Allocation for VLSI Implementation

    Publication Year: 1986, Page(s):4 - 14
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB)

    Generally, in the telecommunication industry, VLSI implementation is viewed as a means to cost reduction and is attempted only after successively decomposing a system into circuits corresponding to individual printed circuit boards (PCB's). This traditional "circuit-design" approach is unable to cope with and to exploit the potential of VLSI capabilities such as chip density and processing power. ... View full abstract»

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  • High-Speed Time Switch Using GaAs LSI Technology

    Publication Year: 1986, Page(s):32 - 38
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    A high-speed time switch using GaAs LSI technology is discussed. A new high-speed time switch structure consisting primarily of shift registers is proposed. This structure requires relatively minimal hardware in designing LSI. As the first stage of study, a GaAs 4-channel time switch LSI is manufactured using this structure. Switching speed of the LSI is 2 Gbits/s and the power consumption 0.64 W/... View full abstract»

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  • A Custom VLSI Chip Set for Digital Signal Processing in High-Speed Voiceband Modems

    Publication Year: 1986, Page(s):81 - 91
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    Systems modems intended for use in relatively large private networks are characterized by high performance, reliability and flexibility to support network management, and multiple modes of operation and user features. This paper describes a programmable digital signal processor which is teamed with a 16-bit microprocessor in a dual processor architecture satisfying the requirements of high-speed v... View full abstract»

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  • VLSI Architectures for the Finite Impulse Response Filter

    Publication Year: 1986, Page(s):92 - 99
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    We review the various VLSI architectures that have been proposed for the finite impulse response filter problem. In addition, new architectures are proposed and improved designs for some of the earlier architectures are developed. View full abstract»

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  • A Theory for the Design of Soft-Error-Tolerant VLSI Circuits

    Publication Year: 1986, Page(s):15 - 23
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    Soft errors caused by ionizing radiation will be a limiting factor in the reliability of VLSI circuits with submicron-feature sizes. A new approach to the design of soft-error-tolerant digital integrated circuits'is presented. It is based on the filtering of transients at register inputs, and it incurs a lower area overhead than known techniques. The method, called soft-error filtering (SEF), is d... View full abstract»

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  • A Study on Pulse Search Algorithms for Multipulse Excited Speech Coder Realization

    Publication Year: 1986, Page(s):133 - 141
    Cited by:  Papers (14)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    This paper describes and compares several kinds of pulse search methods for multipulse excited speech coder realization. These pulse search methods are derived from minimization criterion for errorpower between original speech and synthetic speech, but their performances and required computation amounts are different. Objective and subjective evaluations are carried out to compare the performances... View full abstract»

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  • 400 Mbit/s Optical Regenerator Integrated Circuits

    Publication Year: 1986, Page(s):184 - 191
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    This paper discusses 400 Mbit/s optical regenerator integrated circuits, focusing on their circuit architecture and performance, and describes their application to a 400 Mbit/s optical regenerator. The basic design concepts for high-speed regenerator IC's are discussed and a new integrated circuit architecture based on these design concepts is proposed. The proposed architecture of regenerator IC'... View full abstract»

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  • A 32-Bit Custom VLSI Processor for Communications Network Nodes

    Publication Year: 1986, Page(s):192 - 199
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    Aimed at the application to processors used in communications networks, three kinds of custom CMOS VLSI chips, each integrating approximately 10 kilogates, were developed. During the development of these chips, we overcame various restrictions on the VLSI design, such as input/output pin limitations, bug correction difficulty, and input/output signal delay. A combination of the software and hardwa... View full abstract»

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  • A Discrete Fourier-Cosine Transform Chip

    Publication Year: 1986, Page(s):49 - 61
    Cited by:  Papers (85)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1520 KB)

    An 8-point Fourier-cosine transform chip designed for a data rate of 100 Mbits/s is described. The top-down design is presented step by step, including algorithm modification for VLSI suitability, architectural choices, testing overhead, internal precision assignments, mask generation, and finally, verification of the layout. A high-level language (C) design tool was developed concurrently with th... View full abstract»

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  • VLSI Structures for Viterbi Receivers: Part II--Encoded MSK Modulation

    Publication Year: 1986, Page(s):155 - 159
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    As a specific application of the material presented in Part I, this companion paper identifies VLSI layout strategies for realizing correlative encoded MSK-type Viterbi receivers. When the source symbols are correlatively encoded using a first-order polynomial, the appropriate Viterbi receiver takes the form of a cube-connected cycle (CCC) structure. Second-order encoding polynomials give rise to ... View full abstract»

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Aims & Scope

IEEE Journal on Selected Areas in Communications focuses on all telecommunications, including telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Muriel Médard
MIT