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Solid-State Circuits, IEEE Journal of

Issue 6 • Date Jun 1991

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Displaying Results 1 - 13 of 13
  • A modularized processor LSI with a highly parallel structure for continuous speech recognition

    Publication Year: 1991 , Page(s): 833 - 843
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB)  

    A speech recognition processor CMOS LSI was developed as the processing element (PE) of a ring array processor previously proposed by the authors as architecture to carry out highly parallel recognition processing with array size flexibility. There are three key features for the LSI: (1) a highly parallel I/O structure of triple buffer with cyclical-mode transition control methods to solve the serious problem of inter-PE data transfer overhead versus the array processing; (2) a control structure with two direct memory access (DMA) controllers to realize inter-PE data I/O processing and intra-PE processing in parallel; and (3) a pipelined recognition processing at a high execution rate realized by a pipelined structure and a balanced clock distribution design technique. These effective designs for the PE LSI allow high-speed recognition processing without any inter-PE data transfer overhead in the ring array processor. Combining the PE-LSI architecture with the proposed array architecture for highly parallel dynamic time warping (DTW) processing, a real-time continuous speech recognition system based on continuous dynamic programming matching using the SPLIT method for a 1000-word vocabulary, can be constructed using a ring array processor consisting of 30 PEs View full abstract»

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  • A 1-GIPS Josephson data processor

    Publication Year: 1991 , Page(s): 880 - 883
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    A 4-b data processor with 16-instruction set and 1-kb external-RAM access capability has been designed, fabricated, and tested. Each instruction is treated by a three-stage pipeline of instruction fetch, data fetch, and decode/execute. The chip is operable under a 1-GHz clock, and it has a peak performance of 1 GIPS. The fabrication process is 2.5-μm-rule Nb/AlOx/Nb. An interface circuit to access the all DC-powered 1-kb external-RAM chip is installed. The AC power is utilized with both polarities in each of the four blocks, thus realizing an eightfold serial power supply. Power consumption is 40 mW. Half of the function tests have been completed at low frequency (10 kHz). Part of the processor operated at 1 GHz View full abstract»

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  • Dynamic GaAs capacitively coupled domino logic (CCDL)

    Publication Year: 1991 , Page(s): 844 - 849
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    Dynamic capacitively coupled domino logic (CCDL) has been proposed as a practical means of implementing low-power and high-speed complex gates. The CCDL gate delay characteristics obtained from an analytical model and from test circuits implemented in a 1-μm GaAs E/D process are presented. In addition, the feasibility of using CCDL gates to implement practical circuits is demonstrated by the experimental characterization of a 4-b carry-lookahead adder. The adder has a critical delay of 1.1 ns and a power dissipation of 96 mW. A comparison of the dynamic CCDL adder with conventional static designs indicates the advantages of dynamic CCDL gates in reducing power dissipation and increasing speed, making such gates suitable for VLSI implementations View full abstract»

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  • A 60-GHz NbN single-flux quantum counter circuit

    Publication Year: 1991 , Page(s): 884 - 886
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    A Josephson binary counter using single-flux quanta transitions of DC SQUIDs (superconducting quantum interference devices) has been fabricated using an eight-level NbN-based process. High-speed binary division has been demonstrated at 4.2 K, with single-cell counting observed at 60 GHz using the Josephson voltage-to-frequency relationship. Count rate was primarily limited by conservative process and design rules. The counter was designed for operation at 4.2 K. At 8-10 K, the βL of the SQUIDs would not allow operation, though the junction characteristics were good View full abstract»

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  • A 500-MHz CRT video driver using a linear array

    Publication Year: 1991 , Page(s): 868 - 875
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    A 500-MHz monolithic video driver integrated circuit (IC) for next-generation leading CRT (cathode ray tube) displays with 4 Mpixels or more is presented. The IC has a 320-mA output current amplifier, a video gain controller, a buffered input multiplexer, and a sample-and-hold bias circuit. Using new open-loop amplifier architecture and novel complementary-bipolar circuitry design, the driver IC with bandwidth fB of 500 MHz is fabricated. It is economically implemented by a 2.5-μm commercially available linear array with a transistor fT of 4 GHz. Its f B/fT ratio (a figure of merit of the driver circuit design) is three times larger than that of the latest conventional design. The driver IC and power transistors are intended to realize a high-output (50·Vp-p), wideband (300 MHz) CRT video amplifier characterized by good output voltage stability (<1%) without high-voltage output feedback for DC restoration View full abstract»

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  • Simple and accurate nonlinear macromodel for operational amplifiers

    Publication Year: 1991 , Page(s): 896 - 899
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    A simpler macromodel than that proposed by G. Boyle et al. (1974) is presented. This macromodel does, however, include a large number of operational amplifier characteristics. Advantages of this macromodel include: it is simpler, it is always feasible to calculate parameters, it can be more suitable for AC analysis, and it is quicker to simulate. For the given circuits, the DC analysis with this macromodel was about four times shorter than with the Weil-McNamee (1978) and about two and a half times shorter than with the macromodel of Boyle et al. The duration of transient analysis was up to seven times shorter with the new macromodel than with the Weil-McNamee model, and up to 50% shorter than with the Boyle et al. macromodel View full abstract»

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  • The effects of transistor source-to-gate bridging faults in complex CMOS gates

    Publication Year: 1991 , Page(s): 893 - 896
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 μm there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault View full abstract»

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  • An 8-b slice GaAs bus logic LSI for a high-speed parallel processing system

    Publication Year: 1991 , Page(s): 826 - 832
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7×7-mm2 chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8-μm WNx gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s View full abstract»

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  • Temperature stability of ultrahigh-speed GaAs JFET ICs

    Publication Year: 1991 , Page(s): 886 - 889
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    Ultrahigh-speed digital integrated circuits (ICs) implemented with GaAs/int JFETs are confirmed to be reliable in a wide variety of temperatures. Divide-by-256/258 dual-modulus prescaler ICs using source-coupled FET logic (SCFL) circuits that can operate up to 9 GHz have temperature coefficients of operating frequency stability and input power sensitivity of -17.2 MHz/degree and +0.12 dBm/degree between -20 and +100°C, respectively. Direct-coupled FET logic (DCFL) circuits were also confirmed to have very small temperature coefficients. The variations of the maximum operating frequency and the input power sensitivity of the DCFL divide-by-4 divider IC are -1.93 MHz/degree and +0.47 dBm/degree, respectively, between -60 and +100°C. The variation in the threshold voltage of the JFET is -0.88 mV/degree which is very small for the temperature stability of GaAs digital ICs View full abstract»

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  • Three-region analytical models for MESFETs in low-voltage digital circuits

    Publication Year: 1991 , Page(s): 850 - 858
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    Analytical models for self-aligned gate, GaAs and Si MESFET/JFETs that predict static current-voltage characteristics continuously in three regions of operation (subthreshold, linear, and saturation,) are presented. The characteristic equations are closed-form and describe behavior explicitly in terms of terminal voltages. Comparisons of model predictions with measurements in all regions of device operation are presented. In addition to physical insight into MESFET/JFET operation, the models, due to their relative simplicity, promise digital circuit simulations with accuracy, ease, and efficiency. The models indicate that in typical DCFL (direct-coupled FET logic) circuits MESFETs with undoped substrates are superior to those on highly doped substrates with respect to noise margin considerations View full abstract»

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  • Design considerations for high-frequency crystal oscillators

    Publication Year: 1991 , Page(s): 889 - 893
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    The deleterious effects of crystal shunt capacitance and series resistance on the performance of series-mode oscillators are discussed. When the parasitic capacitance across the crystal significantly modifies the transconductance of the amplifying stage the circuits can become susceptible to a parasitic second mode of oscillation above the series-resonance frequency of the crystal. A simple model that can sufficiently describe such crystal oscillator circuits was developed and used to derive simple design equations that can accurately predict the behavior of these circuits. The design equations should be especially useful for a reliable design in cases when it is not practical to use an additional inductor to compensate for the parasitic shunt capacitance of the crystal. It is shown theoretically that the inclusion of this capacitance in the feedback path reduces the total effective capacitance in the tank circuit, which is tuned to the desired overtone frequency. This creates a second mode of oscillation frequency which is higher than the desired crystal resonance frequency. The ranges of loop-gain and tank resistance values that can prevent this parasitic mode of oscillations are derived. It is also shown that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance View full abstract»

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  • Ultrahigh-speed heterojunction bipolar transistor multiplexer/demultiplexer ICs

    Publication Year: 1991 , Page(s): 876 - 879
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively View full abstract»

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  • An adaptive analog continuous-time CMOS biquadratic filter

    Publication Year: 1991 , Page(s): 859 - 867
    Cited by:  Papers (37)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    An adaptive analog continuous-time biquadratic filter is realized in a 2-μm digital CMOS process for operation at 300 kHz. The biquad implements the notch, bandpass and low-pass transfer functions. The only parameter adapted is the resonant frequency of the biquad, which is identical to the notch frequency and the bandpass center frequency. The update method is based on a least-means-square algorithm which adapts the notch frequency to minimize the power at the notch filter output. The actual update is modified to reduce the circuit complexity to one biquad and one correlator. When the filter is tracking a sinusoid, this update generates a ripple-free gradient that decreases tracking error. Applications include phase-frequency detectors, FM demodulators (linear and frequency shift keying), clock extractors, and frequency acquisition aids for phase-locked loops and Costas loops. Measured results from experimental prototypes are presented. Nonidealities of an all-analog implementation are discussed, along with suggestions to improve performance View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan