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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 1991

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Displaying Results 1 - 15 of 15
  • A fault-tolerant GaAs/CMOS interconnection network for scalable multiprocessors

    Publication Year: 1991 , Page(s): 692 - 705
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1124 KB)  

    The design of an interconnection network (ICN) for a scalable multiprocessor system is presented. The tree-structured network (called SHUNT for scalable hierarchical unidirectional network topology) is organized so that it can be scaled not only in width (through the use of bit slicing), but also in number of ports and in data transfer speed. The network is made from three custom chip types: cluster controller, crossbar switch, and network interface. Implementation of the first prototype chips in 2-μm CMOS is discussed, and the results of detailed circuit simulations for GaAs implementations are given. The network is fault tolerant and is able to detect and correct all single-bit transmission errors. In addition, it can detect failures and reconfigure to work around problems in controllers, port interfaces, or user processors. The network is part of the experimental decoupled computer architect project (DART) currently under study and development View full abstract»

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  • An active resistor network for Gaussian filtering of images

    Publication Year: 1991 , Page(s): 738 - 748
    Cited by:  Papers (48)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB)  

    The architecture of an active resistive mesh containing both positive and negative resistors to implement a Gaussian convolution in two dimensions is described. With an embedded array of photoreceptors, this may be used for image detection and smoothing. The convolution width is continuously variable by 2:1 under user control. Analog circuits implement a 45×40 mesh on a 2-μm CMOS integrated circuit, and perform an entire convolution in 20 μs on applied images View full abstract»

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  • A fault-tolerant array processor designed for testability and self-reconfiguration

    Publication Year: 1991 , Page(s): 778 - 788
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB)  

    The design of a fault-tolerant rectangular array of processing elements (PEs) is presented in which the reconfiguration is done by means of on-chip distributed logic, without the help of any external host. Spare PEs are included in every column of the array, and faulty PEs are bypassed within a column to facilitate reconfiguration in the presence of faults. Scan paths are used to enhance the testability of the array. PEs are tested locally using near-neighbor comparisons without the need of an external host. Because the interconnections between logical neighbors are short, the speed penalty for reconfiguration is very small. Any amount of redundancy can be incorporated in the array without changing the topology of the scheme or the design of the reconfiguration switches. The scheme is well suited for very large-area, high-density chips and wafer-scale integration. In order to demonstrate the capabilities of the scheme and evaluate its performance, an experimental chip consisting of a 6×4 array was designed, fabricated, and tested. Details of the design and the implementation of the chip are presented. The scheme is also analyzed for yield and area utilization for a range of array sizes and PE survival probabilities View full abstract»

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  • A systems approach to custom VLSI for a digital color imaging system

    Publication Year: 1991 , Page(s): 727 - 737
    Cited by:  Papers (5)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1024 KB)  

    An analysis of system requirements is presented that guides the design of a chip set that provides all the required functionality and control for single-sensor color imaging systems. The first device is a color filter array (CFA) processor that processes the single stream of sparse color information from an unconventional CFA pattern and produces a full-resolution color image in real time. The second chip is a red, green, and glue (RGB) processor that improves the image quality of the reconstructed RGB data by performing black-level adjustment, color matrixing, gamma correction, and edge enhancement, again in real time. The third device is a timing controller with an architecture specifically suited to imaging systems. The chips are algorithm specific, and the algorithms, architectures, and design methodology are detailed. The chip set is readily applicable to slide and negative film-to-video converters, electronic still cameras, and component or composite video cameras. It is capable of operation with NTSC, CCIR 601, and PAL/SECAM video standards View full abstract»

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  • Synchronous-mode evaluation of delays in CMOS structures

    Publication Year: 1991 , Page(s): 789 - 795
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    The extension of the explicit formulation of delays in CMOS VLSI to synchronous-mode evaluation allows the accurate evaluation of data path timing (few percent with respect to SPICE simulation) of general CMOS structures for all available input drive configurations, resulting in fast identification of timing problems. A validation of this method has been done using general series parallel networks. It was shown to be sufficiently accurate for resolving race problems. An implementation of the proposed algorithms has been conceived as a preprocessor for an event-driven switch simulator and it has been shown to be fast enough for use in VLSI timing analysis View full abstract»

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  • High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic

    Publication Year: 1991 , Page(s): 749 - 762
    Cited by:  Papers (14)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    A high-performance standard cell library for the Tektronix advanced bipolar process GST1 has been developed. The library is targeted for the 250-MIPS (million instructions per second) fast reduced instruction set computer (FRISC) project. The GST1 devices have a minimal emitter size of 0.6 μm×2.4 μm and a maximum f t of 15.5 GHz. By combining advanced bipolar technology and high-speed differential logic, gate propagation delays of 90 ps can be achieved at a power dissipation of 70 mW. The fastest buffers/inverters have a propagation delay of only 68 ps. A 32-b ALU (arithmetic and logic unit) partitioned into four slices can perform an addition in 3 ns using differential standard cells with improved emitter-follower outputs and fast differential I/O drivers. A modeling technique for high-speed differential current tree logic is introduced. The technique gives accurate timing information and models the transient behavior of current trees View full abstract»

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  • A single-chip pipelined 2-D FIR filter using residue arithmetic

    Publication Year: 1991 , Page(s): 796 - 805
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    Novel circuits and architecture for residue arithmetic are presented. These circuits are designed for fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. Substantial area savings have resulted. The circuits include a residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3×3, finite impulse response (FIR), variable coefficient, linear phase filter has been designed and fabricated in standard 2-μm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this combination is the possible tradeoff available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6×4.2 mm2, dissipates 220 mW of power, and is synchronized with a 180-ns clock cycle View full abstract»

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  • High-speed low-power charge-buffered active-pull-down ECI circuit

    Publication Year: 1991 , Page(s): 812 - 815
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed View full abstract»

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  • Two bandpass active filters with reduced sensitivities

    Publication Year: 1991 , Page(s): 816 - 819
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    A current-controlled current source and a voltage-controlled voltage source are used in conjunction with four passive components to implement second-order bandpass filters. The circuits, which exhibit reduced values for their active and passive sensitivities, can be used in a very large frequency range when the active elements are designed from high-performance bipolar arrays. Simulated results using SPICE, which confirm the theoretical analysis, are reported and discussed for active elements implemented in a translinear form. Experimental results are given indicating that the implementation compares favorably with conventional ones View full abstract»

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  • Multiple-level partitioning: an application to the very large-scale hardware simulator

    Publication Year: 1991 , Page(s): 706 - 716
    Cited by:  Papers (5)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    With modern technology, a very-large-scale system may contain several million gates. To achieve an optimal multiple-level partitioning of such a system onto a fixed hierarchy hardware accelerator presents a formidable challenge to even the fastest computing engines currently available. The application of a divide-and-conquer heuristic coupled with a novel ratio-cut algorithm that solves the above problem under a variety, of constraints is described. The goal of this approach is to minimize the communication cost in the hierarchy. Experiments with designs containing up to two million gates are described, and it is demonstrated that the proposed approach decreased communication costs by a factor of two or more when compared with other approaches. This approach enables the hardware simulator to perform approximately three billion gate evaluations per second. or approximately 200 million event evaluations in an event-driven simulator, using a 6% activity rate View full abstract»

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  • A silicon model of an auditory neural representation of spectral shape

    Publication Year: 1991 , Page(s): 772 - 777
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    An analog integrated circuit that implements an auditory neural representation of spectral shape is described. The circuit contains silicon models of the cochlea, inner hair cells, spiral ganglion cells, and the neurons that compute an amplitude-invariant representation of spectral shape. The chip uses the temporal information in each silicon auditory nerve fiber to compute this final representation. The chip was fabricated and fully tested. Data comparing the silicon auditory nerve representation and the final representation are presented. The 9000-transistor chip computes all outputs in real time using analog continuous-time processing View full abstract»

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  • Loop-based design and reconfiguration of wafer-scale linear arrays with high harvest rates

    Publication Year: 1991 , Page(s): 717 - 726
    Cited by:  Papers (6)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    Design and reconfiguration approaches for high harvest rates and parallel on-wafer diagnosis of linear arrays are described. The defect-tolerant designs use multiplexers to switch intercell connections and guarantee that the wire length between any two logically adjacent cells is constant, independent of fault distribution. The designs are appropriate for implementing linear arrays of wafer-scale memory and processor architectures. The harvesting of fault-free cells into a linear array is a percolation process; there exists a critical cell yield such that the harvest rate drops to zero (approaches 100%) if the cell yield is below (above) the critical value. Finding a maximum-size linear array for a given set of fault-free cells is polynomial time solvable if only the interconnections between fault-free cells are utilized, but is NP-complete if the interconnections between all cells are utilized. A heuristic reconfiguration algorithm utilizing the interconnections between all cells is presented. Application of boundary scan to parallel testing and on-wafer diagnosis of the arrays is described View full abstract»

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  • Multilevel optimization in the design of a high-performance GaAs microcomputer

    Publication Year: 1991 , Page(s): 763 - 767
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer View full abstract»

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  • VLSI partitioning of a 2-Gs/s digital spectrometer

    Publication Year: 1991 , Page(s): 768 - 772
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    A digital correlating spectrometer for radioastronomy that is based on a custom GaAs digitizer and a custom micropipelined CMOS correlator is described. The digitizer quantizes at two gigasamples per second (Gs/s) and 2-b resolution. A GaAs demultiplexer distributes the data into eight parallel streams of 250 Ms/s each. The CMOS correlator operates at 250 Ms/s using 20 mW per correlator lag. The correlator output is processed on a host microcomputer to create a 1-GHz spectrum of the input signal that can be displayed interactively. An 8×9-mm chip is being developed in a 2-μ process that contains 320 correlator lags. The design is partitioned into GaAs and CMOS components according to the required throughput at each stage of the system. The fastest signals (2 GHz) are kept on the chip level to minimize delay, crosstalk, system noise, and power consumption. Moderate-speed signals (250 MHz) are driven by GaAs components. CMOS components are used where high-speed outputs are not required. A strong synergy between the correlator architecture and micropipelined CMOS technology improves the performance by an order of magnitude compared to existing designs. Preliminary correlator chips have been built and tested at 250 Ms/s; final chips are under design View full abstract»

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  • A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array

    Publication Year: 1991 , Page(s): 806 - 811
    Cited by:  Papers (10)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A 3-ns-range, 8-ps-resolution timing generator LSI has been realized by using Si bipolar gate arrays. By adopting a redundant weighted delay-unit matrix based on a process-insensitive polynomial formulation, ±2-ps linearity error has been attained at input clock rates of up to 700 MHz. Thermal noise and interconnection crosstalk have been quantitatively investigated as critical factors causing timing error. By adopting the results to the circuit and layout design, thermal jitter and systematic timing error due to crosstalk were successfully suppressed to less than 8 and ±5 ps. respectively View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan