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IEEE Transactions on Computers

Issue 5 • Date May 1988

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Displaying Results 1 - 16 of 16
  • Fault-tolerant FFT networks

    Publication Year: 1988, Page(s):548 - 561
    Cited by:  Papers (155)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log2N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of fa... View full abstract»

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  • Synchronizing transactions on objects

    Publication Year: 1988, Page(s):541 - 547
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    A method is discussed for synchronizing operations on objects when the operations are invoked by transactions. The technique, which is motivated by a desire to make use of possible concurrency in accessing objects, takes into consideration the granularity at which operations affect an object. A dynamic method is presented for determining the compatibility of an invoked operation with respect to op... View full abstract»

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  • Product-form solution techniques for the performance analysis of multiple-bus multiprocessor systems with nonuniform memory references

    Publication Year: 1988, Page(s):532 - 540
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    Recursive relations are derived for the exact computation of the steady-state probability distribution of some queuing models with passive resources that can be used to analyze the performance of multiple-bus multiprocessor system architectures. The most general case that can be shown to admit a product-form solution is described, and a recursive solution is obtained taking into account, consideri... View full abstract»

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  • A fault-tolerant FFT processor

    Publication Year: 1988, Page(s):617 - 621
    Cited by:  Papers (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A method is proposed for achieving fault tolerance by introducing a redundant stage for a special-purpose fast Fourier transform (FFT) processor. A concurrent error-detection technique, called recomputing by alternate path, is used to detect errors during normal operation. Once an error is detected, a faulty butterfly can be located with log (N +5) additional cycles. The method has 100% d... View full abstract»

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  • Optimal assignments in broadcast networks

    Publication Year: 1988, Page(s):521 - 531
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    A program whose execution is distributed among several processors in a broadcast system has a total execution cost equal to the sum of processor costs and communication costs, which are functions of the amount of data transmitted and the average transmission delays. A critical delay x is a value of average transmission delay such that no assignment is minimum-cost for average delays both ... View full abstract»

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  • The Kappa network with fault-tolerant destination tag algorithm

    Publication Year: 1988, Page(s):612 - 617
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The design of the Gamma network is analyzed in terms of block structure. The analysis reveals the asymmetry of its duplicate links, and an alternate design in the form of the Kappa network is proposed. Its novel feature is the symmetry of duplicate links at the block level. This symmetry results in a simple control algorithm and enhanced fault tolerance. The relationship between the Kappa network ... View full abstract»

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  • The IBM System/370 vector architecture: design considerations

    Publication Year: 1988, Page(s):509 - 520
    Cited by:  Papers (20)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1200 KB)

    The considerations that shaped the architecture of the IBM System/370 Vector Facility are reviewed. The architectural requirements, decisions, and innovations are summarized, and the rationale for the choices that were made is given. Issues related to vector function, performance, compatibility, migration, and integration with the rest of the System/370 architecture are covered View full abstract»

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  • Modulo 3 residue checker: new results on performance and cost

    Publication Year: 1988, Page(s):608 - 612
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The resid... View full abstract»

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  • On the augmented data manipulator network in SIMD environments

    Publication Year: 1988, Page(s):574 - 584
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    Formulas for the number of the augmented-data-manipulator (ADM)-passable permutations were given previously as cross-recurrence relations for the cardinalities of three specific subsets of such permutations. More concise, transparent recurrence formulas are derived utilizing a novel and conceptually simple model of the ADM. As a byproduct, a global control algorithm for the inverse ADM (IADM) is o... View full abstract»

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  • The cubical ring connected cycles: a fault tolerant parallel computation network

    Publication Year: 1988, Page(s):632 - 636
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    The cube-connected cycles network is suitable for realization in VLSI, since it satisfies the properties of degree boundedness of the nodes (=3), and regularity of layout. Another network called the cubical ring-connected cycles (CRCC) is proposed that has all the desirable features of the cube-connected cycle (CCC) and is single-cycle fault tolerant as well. The degree of each processor is less t... View full abstract»

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  • Incomplete hypercubes

    Publication Year: 1988, Page(s):604 - 608
    Cited by:  Papers (172)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Since a k-dimensional hypercube has 2k vertices, these systems are restricted to having exactly 2k computing nodes. Because system sizes must be a power of two, there are large gaps in the sizes of systems that can be built with hypercubes. Routing and broadcast algorithms are presented for hypercubes that are missing certain of their nodes, called incomplete hypercu... View full abstract»

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  • Implementing precise interrupts in pipelined processors

    Publication Year: 1988, Page(s):562 - 573
    Cited by:  Papers (119)  |  Patents (155)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1216 KB)

    Five solutions to the precise interrupt problem in pipelined processors are described and evaluated. An interrupt is precise if the saved process state corresponds to a sequential model of program execution in which one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an instruction may be initiated before its predecessor... View full abstract»

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  • A fault-tolerant systolic sorter

    Publication Year: 1988, Page(s):621 - 624
    Cited by:  Papers (55)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    A fault-tolerant systolic sorter design is proposed. An algorithm-based fault tolerance is achieved by testing the invariants of a systolic sorter during normal operation. Transient and permanent computation errors can be detected by using error-checking code and some redundant cells. A block with a single faulty cell can be located. Small hardware overhead and negligible time overhead are shown t... View full abstract»

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  • Equilibrium point analysis of memory interference in multiprocessor systems

    Publication Year: 1988, Page(s):585 - 593
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    An approximate analytic tool called equilibrium point analysis is applied to the problem of memory interference in multiprocessor systems. It is a simple and powerful analytic tool based on the fluid approximation and has been widely used for packet broadcast systems. It is shown that quite general multiprocessor systems can be studied quite simply with this technique, these systems include those ... View full abstract»

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  • Layer assignment problem for three-layer routing

    Publication Year: 1988, Page(s):625 - 632
    Cited by:  Papers (36)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets so that the number of vias is minimized. The problem is often referred to as the via minimization problem. The problem is considered for three-layer routing, concentrating on one version called the constrained via minimization (CVM3) problem. It is shown that the CVM3 ... View full abstract»

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  • Processor utilization in a linearly connected parallel processing system

    Publication Year: 1988, Page(s):594 - 603
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    The authors study the problem of assigning program fragments to a system of processing elements in which low-level operations are performed in parallel. Such a system is said to be linearly connected if each processing element can only communicate directly with its two nearest neighbors. They show that the problem of determining whether a perfect assignment exists is NP-complete but can be solved ... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org