By Topic

Parts, Hybrids, and Packaging, IEEE Transactions on

Issue 3 • Date September 1973

Filter Results

Displaying Results 1 - 10 of 10
  • Who's Who in G-PHP

    Page(s): 142
    Save to Project icon | Request Permissions | PDF file iconPDF (132 KB)  
    Freely Available from IEEE
  • Foreword

    Page(s): 143
    Save to Project icon | Request Permissions | PDF file iconPDF (88 KB)  
    Freely Available from IEEE
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Novel Planar Multilevel Interconnection Technology Utilizing Polyimide

    Page(s): 176 - 180
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    A completely new planar method permitting step-free multilevel interconnections is proposed. The key role in this technique is played by the polyimide film which is used as insulating layers. The fluid property of the polymer solution always gives an ideal flatness to the surface of the wafer no matter how many steps are formed by preceding metallization processes. Using this planar metallization with polymer (PNIP) technique, a five-level structure which consists of five metal (aluminum) and five polyimide layers has been successfully made, The PMP structure completely eliminates the failures which result from open circuits between metal layers at crossovers and via-holes and from short circuits between metal layers through the pin-holes of insulating layers. No trace of degradation is observed in the characteristics of the MOS-FET covered with the polyimide either after heating at 150°c for 2000 hours or after a bias-temperature test at 125°c for 200 hours. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fabrication of Multilayer Ceramic Capacitors by Metal Impregnation

    Page(s): 144 - 147
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    Ceramic units were fabricated having internal porous layers which extend to two edge faces of the units. The porous layers were analogous to the internal noble metal electrode layers of conventional ceramic multilayer capacitors. By impregnating the porous regions with conductive materials such as Ag, Pb, or Sn, capacitors were formed. Scanning electron microscopy was used to examine the structures of the porous regions and of the impregnated metals. An end termination technique was developed for use with injected internal electrodes of low melting point metals Units were made having electrical characteristics similar to conventionally prepared units with noble metal internal electrodes. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Processing and Performance of Tantalum Nitride Thin Film Resistor Networks with ±50 Ppm/°C TCR

    Page(s): 155 - 160
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    Vacuum annealing has bean used to routinely manufacture tantalum nitride resistor networks with temperature coefficients in the range of ±50 ppm/°oC. The as-sputtered temperature coefficient of resistance (TCR) of tantalum nitride films with nitrogen content set for optimum stability is approximately --130 ppm. Although near zero TCR's can be obtained by reducing the nitrogen content during sputtering, such films exhibit substantial negative changes when dc loaded. Networks were fabricated on aluminum oxide substrates using in-line sputtered tantalum nitride films and vacuum evaporated chrome-gold conductive termination films. Anneal schedules (to remove structural defects) in the range of 460°C to 510°C for 4 h were found suitable for producing films with near zero TCR over a sheet resistance range of 30-75 \Omega /square. Conventional photolithography techniques were used to delineate resistor networks with up to 20 resistors per network. After a thermal stabilization of 16 h at 250°c, the resistors were anodized to ratio tolerances as close as 0.05%. Resistances of 50 \Omega to 20 k \Omega were manufactured on a single network. Load life and thermal aging results indicate no degradation in performance as a result of shifting the TCR by vacuum annealing. Temperature cycle changes were less than 0.01%. Resistor TCR tracking was less then 7 ppm/°C on 0.700 X 0.700 network. Resistor noise was measured and found not to differ from unannealed resistor films. By incorporating the vacuum annealing step into the standard tantalum nitride manufacturing process, resistor networks with near zero TCR can be produced with the same excellent stability possessed by unannealed films. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Bilevel Thin Film Hybrid Circuit Containing Crossovers, Resistors, Capacitors, and Integrated Circuits

    Page(s): 181 - 185
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    Here is a discussion on the fabrication, characterization, and economic considerations of a set of complex hybrid integrated circuits being used in exploratory switching applications. Several approaches to fabrication are discussed. One approach is unique in that it includes four distinct technologies in addition to simple thin film interconnections. They are (1) beam crossovers, (2) thin film resistors, (3) thin film capacitors, and (4) metallized via holes to a backplane. Alternate approaches including discrete capacitor elements are also discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An SiO2-Ta2O5Thin Film Capacitor

    Page(s): 161 - 166
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    A capacitor has been developed which is superior to previously reported duplex capacitors. The dielectric consists of anodic tantalum oxide overlaid with silicon dioxide deposited by RF sputtering. This capacitor proved usefuI as a low-valued capacitor Of capacitance density ranging from 150 pF/mm2to 20 pF/mm2, corresponding to a thickness range of a silicon dioxide film from 0.2 µ/m to 2.0µm. The capacitor can be produced with very high yield Of approximately 100%, due to the defect-free anodic oxide film diminishing the importance of defects inevitably induced in the RF sputtered silicon dioxide film. The silicon dioxide film can be deposited without causing any deterioration of the anodic film of tantalum oxide by Control of the RFsputtering conditions. The capacitor remained stable with no failures occurring when aged under various conditions of voltage, temperature, and humidity. The capacitor can be processed in a manner compatible with the manufacturing process of the TM or TMM capacitor. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Powder Geometry and Structural Design of the High Volumetric Efficiency Tantalum Electrolytic Capacitor

    Page(s): 148 - 155
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB)  

    The influence of powder geometry on the performance of tantalum electrolytic capacitors was investigated over a range of conditions. Two design normalizations were chosen to compare measurements with a transmission line model. To a first order approximation the results are as predicted by theory. Ano'malies appear in the behavior of capacitance and the equivalent series resistance (ESR) under extreme conditions. Powder geometry and anode size also give second order effects. The findings are useful in capacitor design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal Response of Microwave Transistors Under Pulsed Power Operation

    Page(s): 185 - 193
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1296 KB)  

    The transient temperature response and thermal profiles near the junction of a transistor or other semiconductor device are nearly impossible to measure experimentally. These response characteristics can be accurately predicted, however, through the use of computeraided simulation. In this paper results from the simulation of two microwave power transistors are presented and discussed. In particular, the first device contains a single large junction area, and the second contains multiple junction areas. Thermal characteristics within the chip itself, that is, from the transistor junction to the chip .carrier, are emphasized. This region usually contains, by far, the greatest fraction of the total \Delta T between the junction and the final heat sink, especially under pulsed power operation. Transient temperature response curves, internal temperature distributions and the effects of temperature dependent material properties are described. The effects of varying the power dissipation rate, pulse length and duty cycle are shown, and final1y, methods of improving heat transfer, such as the use of a diamond heat-spreader, are discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Transaction ceased production in 1977. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope