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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb 1991

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Displaying Results 1 - 12 of 12
  • Clustered defects in IC fabrication: Impact on process control charts

    Page(s): 36 - 42
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    In IC fabrication, standard process control charts for defects often sound many false alarms, i.e. the chart incorrectly indicates that the process is out of control. It is pointed out that when non-Poisson behavior is encountered in defect data, it is necessary to determine whether this is due to an out-of-control manufacturing process or a manufacturing or data collection procedure that yields clustered defect counts. A procedure that includes the outlier removal method to discriminate between clustered defect data and a process that is out of control is proposed, and its application to two sets of real-world data is shown. One is an example from IC manufacturing where true clustering exists, and the other is a manufacturing example where persistent out-of-control conditions give the appearance of clustering. Simulation results indicate that the procedure works well within reasonable boundaries. A method for constructing defect control charts for processes that yield clustered defects is also presented View full abstract»

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  • Generation of electromigration ground rules utilizing Monte Carlo simulation methods

    Page(s): 63 - 66
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    A novel method is presented for determining ground rule limits for the maximum current allowed in a metal line based on the electromigration and process parameters. A Monte Carlo technique is utilized to simulate the distribution of metal width, metal thickness, and electromigration properties to determine the maximum current allowed for a given failure criterion. In linewidths of less than 6 μm, the Monte Carlo method doubles the allowed current compared to the worst-case linewidth approach. Thus, increased currents are allowed in metal lines without sacrificing predetermined reliability goals. It is also demonstrated that the accuracy of the Monte Carlo simulation is based on the number of iterations executed. Specifically, it is shown that the accuracy of the simulation is dependent on the number of outer loop iterations performed View full abstract»

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  • Selective electroless plating-A new technique for GaAs MMICs

    Page(s): 69 - 72
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    A simple, cost-effective processing technique, selective electroless plating, is proposed for GaAs monolithic microwave integrated circuits (MMICs). Microwave measurements show that the attenuation properties of transmission lines fabricated by this processing technique are comparable to the attenuation properties of lines fabricated by the traditional evaporation lift-off technique View full abstract»

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  • Radiation thermometry of silicon wafers in a diffusion furnace for fabrication of LSI

    Page(s): 59 - 63
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    A radiation thermometry technique suitable for measuring the temperature of silicon wafers in a diffusion furnace has been developed. A principal feature of this technique is that it measures the temperature of wafers that are not in the line of sight of a conventional pyrometer. An optical guide, consisting of two quartz prisms, gives optical access to interior wafers in the load. A measuring wavelength of 0.9 μm is selected since a silicon wafer is opaque and its emissivity does not depend on temperature at this wavelength. The accuracy of the thermometry is examined by comparing the measured value of the pyrometer with that of a thermocouple. The two measured values agree within ±2°C in a steady state. When wafers are being inserted into or drawn out from the furnace, however, an error is caused by the veiling glare at the optical guide and the wafer View full abstract»

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  • Continuous equipment diagnosis using evidence integration: an LPCVD application

    Page(s): 43 - 51
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    A diagnostic system that employs the Dempster-Shafer (D-S) evidential reasoning technique to conduct malfunction diagnosis on semiconductor manufacturing equipment has been developed. This is accomplished by combining the continuous stream of information that originates from maintenance status records, from real-time sensor measurements, and from the differences between inline measurements and values predicted by equipment models. Using this information, equipment malfunctions are analyzed and their causes are inferred through the resolution of qualitative and quantitative constraints. The qualitative constraints describe the normal operation of the equipment. The quantitative constraints are numerical models that apply to the manufacturing step in question. These models are specifically created and characterized through experimentation and statistical analysis, and they can be updated to reflect equipment aging. The violation of these constraints is linked to the evaluation of continuous belief functions for the calculation of the belief associated with the various types of failure. The belief functions encapsulate the experience of many equipment maintenance specialists. Once created, the belief functions can be fine-tuned automatically, drawing from historical maintenance records. These records are stored in symbolic form to facilitate this task, and they must be updated to track equipment changes over time. A prototype of this diagnostic system was implemented in an object-oriented programming environment. The effectiveness of this technique was demonstrated on a low-pressure chemical vapor deposition (LPCVD) reactor used for the deposition of undoped polysilicon View full abstract»

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  • Principles of wet chemical processing in ULSI microfabrication

    Page(s): 26 - 35
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    Fine patterning technology for integrated device manufacturing requires properties such as surface cleanliness, surface smoothness, complete uniformity, and complete etching linearity in wet chemical processing. An improved chemical composition for buffered hydrogen fluoride (BHF:NH4F+HF+H2O) is determined based on fundamental research into the chemical reaction mechanism of BHF and SiO 2. Advanced wet chemical processing based on investigation of chemical reaction mechanisms and properties of liquid chemicals, concentrating on the SiO2 patterning process by BHF, is described. The principles of wet chemical processing in silicon technology are based on the following: the determination of the dominant reaction (etching) species, the influence of the solubility of the etching products in BHF on etching uniformity and linearity, stability of chemical composition without solid-phase segregation, and an improvement of the wettability of liquid chemicals on the wafer surface by the addition of a surfactant View full abstract»

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  • Capless rapid thermal annealing of GaAs using a graphite susceptor

    Page(s): 21 - 25
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    The results of experiments performed to evaluate the use of a commercially available rapid thermal annealer (RTA) with a graphite susceptor for capless rapid thermal annealing to activate implants in GaAs are reported. The interior of the susceptor was easily charged with As by annealing a sacrificial GaAs wafer. Wafers annealed face up in the charged susceptor showed no evidence of surface degradation (due to preferential loss of As) and no decrease in implant activation (peak doping) when compared to dielectric (SiO2) capped anneals. Over 50 wafers have been annealed without recharging the susceptor. In addition, slip on 3-in wafers was almost completely eliminated due to the reduction of radial temperature gradients. It is concluded that capless RTA in a commercially available graphite susceptor appears to be a viable annealing technique for activating implants in GaAs and related III-V materials and is suitable for a production environment View full abstract»

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  • A hybrid wafer-dicing process for GaAs MMIC production

    Page(s): 66 - 68
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    A dicing process for GaAs MMIC (monolithic microwave integrated circuit) wafers using spin-on wax for wafer mounting and a hybrid process of wet chemical etching/mechanical sawing for chip dicing is described. This process minimizes ragged chip edges and reduces generation of microcracks in addition to the elimination of the plated gold burrs on the backside of the diced MMIC chips. This process gives a uniformity of -3 μm across a 2-in wafer following the completion of the whole backside process. This GaAs chip dicing technique is amenable to production because it exhibits both a very high chip yield (>90%) and nearly flawless edges View full abstract»

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  • Steady-state thermal uniformity and gas flow patterns in a rapid thermal processing chamber

    Page(s): 14 - 20
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    The steady-state temperature distribution and gas flow patterns in a rapid thermal processing system are calculated numerically for various process conditions. The results are verified by comparison to experimental epitaxial growth rate data. The gas flow patterns and temperature distributions depend strongly on pressure and ambient composition. Steady-state uniformity is found to be described to first order by the radiant uniformity at the wafer surface and substrate heat flow considerations alone. For high-thermal-uniformity systems, however, convective cooling does play an important role, approximately equal to that of edge losses View full abstract»

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  • Use of influence diagrams and neural networks in modeling semiconductor manufacturing processes

    Page(s): 52 - 58
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    An adaptive learning architecture for modeling manufacturing processes involving several control variables is described. The use of this architecture to process modeling and recipe synthesis for deposition rate, stress, and film thickness in low-pressure chemical vapor deposition (LPCVD) of undoped polysilicon is discussed. In this architecture the model for a process is generated by combining the qualitative knowledge of human experts, captured in the form of influence diagrams, and the learning abilities of neural networks for extracting the quantitative knowledge that relates the parameters of a process. To evaluate the merits of this methodology, the accuracy of these new models is compared to that of more conventional models generated by the use of first principles and/or statistical regression analysis. The models generated by the integration of influence diagrams and neural networks are shown to have half the error or less, even though given only half as much information in creating the models. Furthermore, it is shown that, by employing the generalization ability of neural networks in the synthesis algorithm, new recipes can be produced for the process. Two such recipes are generated for the LPCVD process. One is a zero-stress polysilicon film recipe; the second is a uniform deposition rate recipe which is based on the use of a nonuniform temperature distribution during deposition View full abstract»

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  • A model for rapid thermal processing: achieving uniformity through lamp control

    Page(s): 9 - 13
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    A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures View full abstract»

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  • Manufacturability issues related to transient thermal annealing of titanium silicide films in a rapid thermal processor

    Page(s): 1 - 8
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    Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSix films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSix films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721