By Topic

IEEE Design & Test of Computers

Issue 1 • March 1991

Filter Results

Displaying Results 1 - 8 of 8
  • Concurrent engineering in product development

    Publication Year: 1991, Page(s):6 - 13
    Cited by:  Papers (16)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (946 KB)

    Concurrent engineering, an integrated design approach that considers, from the outset, all elements of the product life cycle from conception through disposal, including quality, cost, schedule, and user requirements, is examined. A description is given of the US Defense Advanced Research Projects Agency DICE program, which is aimed at promoting the practice and acceptance of concurrent engineerin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simulation-based verification for high-level synthesis

    Publication Year: 1991, Page(s):14 - 20
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1299 KB)

    The verification problem is described, and a way to verify a high-level synthesis system automatically is presented. The system, called Satya, maps an algorithmic description to a logic circuit description and compares descriptions to detect semantic errors and identify the cause of those errors. Satya has been used to verify the Bridge synthesis system, which accepts a subset of C as input, but t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The compiled logic simulator

    Publication Year: 1991, Page(s):21 - 34
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1911 KB)

    A two-value, zero-delay simulator that computes signatures and analyzes fault coverage for circuits with built-in self-test (BIST) is described. The simulator, called the compiled logic simulator (CLS), is used with a monitor that simulates BIST control logic at a high level. The simulator's compiled code is well suited to the IBM 3090 pipeline and fault simulation using flat random patterns. The ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Object programming for CAD

    Publication Year: 1991, Page(s):35 - 42
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1235 KB)

    The use of object-oriented programming to simplify the design and implementation of CAD systems is discussed. The three features common to all languages that support object-oriented programming data abstraction, inheritance, and runtime-function determination are examined. Examples are given to illustrate the advantages of object-oriented methods. How to build an embryonic CAD framework and when t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VHDL as input for high-level synthesis

    Publication Year: 1991, Page(s):43 - 49
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (961 KB)

    High-level synthesis is defined, and the feasibility of high-level synthesis from a behavioral, sequential description in VHDL (VHSIC hardware description language) is examined. It is seen that in some cases the semantics and descriptive power of the language create difficulties for high-level synthesis, and in other cases the high-level synthesis framework used imposes limitations. Restrictions i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A rule-based design-for-testability rule checker

    Publication Year: 1991, Page(s):50 - 57
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    An automatic design-for-testability (DFT) rule checker that can be used during early design stages at the register-transfer level is described. The system uses expert-system technology to check the correspondence of a rule set to a register-transfer level description of the design. In addition, it runs quickly and interactively, supports hierarchical design by checking subcircuits and groups of su... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fail-safe interlocking system for railways

    Publication Year: 1991, Page(s):58 - 66
    Cited by:  Papers (10)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (997 KB)

    A new approach to the design of microprocessor-based failsafe systems for railways that was used to design the FIRM architecture is described. The approach involves assigning appropriate levels of safety to system functions, depending on how critical they are, instead of using the same safety standard for all functions. The FIRM (short for failsafe interlocking system for railways using microproce... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Designing a real-time coprocessor for Ada tasking

    Publication Year: 1991, Page(s):67 - 79
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1659 KB)

    A VLSI coprocessor that radically improves the real-time performance of the Ada tasking model, especially the rendezvous, is discussed. An overview of multilevel design is given, and design levels and models are examined. A description is given of the design strategy, which entails stepwise refinement of functional models representing the coprocessor at more and more detailed levels. A chip was ge... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty