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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • Date Apr 1991

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Displaying Results 1 - 16 of 16
  • Nonlinear transformer model for circuit simulation

    Publication Year: 1991, Page(s):476 - 482
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    A transformer model which consists of a nonlinear core with hysteresis and multiple windings is described as implemented in DSPICE. In contrast to previous implementations, the nonlinear behavior of the new model is described by continuous piecewise-hyperbolic functions characterized by three parameters. These parameters are the same as parameters previously published in the literature. A loop-tra... View full abstract»

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  • Distributed genetic algorithms for the floorplan design problem

    Publication Year: 1991, Page(s):483 - 492
    Cited by:  Papers (51)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1012 KB)

    Designing a VLSI floorplan calls for arranging a given set of modules in the plane to minimize the weighted sum of area and wire-length measures. A method of solving the floorplan design problem using distributed genetic algorithms is presented. Distributed genetic algorithms, based on the paleontological theory of punctuated equilibria, offer a conceptual modification to the traditional genetic a... View full abstract»

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  • Numerical analysis of magnetic-field-sensitive bipolar devices

    Publication Year: 1991, Page(s):501 - 511
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1044 KB)

    Two-dimensional numerical solutions to the system of partial differential equations governing galvanomagnetic carrier transport in magnetic-field-sensitive integrated bipolar transistors are presented. The equations are discretized using the finite box procedure with a variation in the standard Scharfetter-Gummel approach adopted for the current continuity equations. High-resolution computations o... View full abstract»

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  • Is redundancy necessary to reduce delay?

    Publication Year: 1991, Page(s):427 - 435
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    The question of whether single stuck-at-fault redundancies are necessary to increase performance or whether they are only an unnecessary by-product of performance optimization is addressed. A constructive resolution of this question is given in the form of an algorithm that takes as input a combinational circuit and returns an irredundant circuit that is as fast. The utility of this algorithm is d... View full abstract»

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  • Multilevel logic synthesis of symmetric switching functions

    Publication Year: 1991, Page(s):436 - 446
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1012 KB)

    Designs of totally symmetric functions provided by logic synthesis systems have on average more than twice as many literals as best designs, while the designs of nonsymmetric functions have on average 20% more literals. A simple, but effective, heuristic method for synthesizing symmetric functions that detects and takes advantage of symmetry and is based on classic disjoint decomposition theory is... View full abstract»

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  • A layout modification approach to via minimization

    Publication Year: 1991, Page(s):536 - 541
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    The approach is to eliminate vias systematically by modifying the routing layout. The algorithm was implemented and applied to benchmark routing layouts published in the literature. Significant reduction in the number of vias was obtained without increasing the routing area. The experimental results show that the algorithm is more effective in via reduction and more efficient in running time than ... View full abstract»

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  • N-channel MOSFET model for the 60-300-K temperature range

    Publication Year: 1991, Page(s):512 - 518
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    An engineering model of the short-channel NMOS transistor which is applicable to both room-temperature and cryogenic device operation is presented. The model incorporates the nonuniversal dependence of the effective channel mobility on the effective vertical field, which is ignored in room-temperature device models. Described also is a novel method to account for the bulk charge effect in the pres... View full abstract»

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  • An integrated CAD system for algorithm-specific IC design

    Publication Year: 1991, Page(s):447 - 463
    Cited by:  Papers (58)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2116 KB)

    LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. ... View full abstract»

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  • Efficient simulation of MOS circuits

    Publication Year: 1991, Page(s):541 - 544
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Novel techniques are described which significantly speed up classical circuit simulation of MOS LSI circuits. By taking advantage of the unilateral properties of MOS transistors, modifications of Newton's method are developed, reducing the computational effort for the Gaussian elimination mainly for large circuits. Latency is another property of MOS circuits which can be exploited to enhance simul... View full abstract»

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  • Combinatorial optimization by stochastic evolution

    Publication Year: 1991, Page(s):525 - 535
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB)

    A novel technique is introduced, called stochastic evolution (SE), for solving a wide range of combinatorial optimization problems. It is shown that SE can be specifically tailored to solve the network bisection, traveling salesman, and standard cell placement problems. Experimental results for these problems show that SE can produce better quality solutions than sophisticated simulated annealing ... View full abstract»

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  • A tool for hierarchical test generation

    Publication Year: 1991, Page(s):519 - 524
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    An extended system MSST (MIMOLA software system test generator), and its algorithms for automatic test generation are presented. In a hierarchical, mixed-level approach (from gate to system level) test patterns for sequential circuits and test programs for external testing or self-testing (diagnostics) of microprocessor boards or processor systems can be generated automatically. In a complete hier... View full abstract»

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  • DARSI: RC data reduction [VLSI simulation]

    Publication Year: 1991, Page(s):493 - 500
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    Taking into account RC effects in VLSI simulation and verification systems, without seriously degrading their efficiency, requires preliminary data reduction. A tool, DARSI (data reduction system for interconnects), that can handle both polysilicon and diffusion resistive effects is presented. It contains the reduction scheme described by S.-L. Su et al. (Proc. IEEE Conf. Computer-Aided D... View full abstract»

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  • Reduced offsets for minimization of binary-valued functions

    Publication Year: 1991, Page(s):413 - 426
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1148 KB)

    A modified approach to two-level logic minimization is described which obviates the need to compute the offset, yet provides the same global picture available with the offset. This approach is based on a new concept called the reduced offset. It is shown that reduced offsets can be computed without using the offset. This scheme has been implemented in ESPRESSO with an interface to the multilevel m... View full abstract»

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  • A method of reducing aliasing in a built-in self-test environment

    Publication Year: 1991, Page(s):548 - 553
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    A method of reducing aliasing in built-in self-test of VLSI circuits is proposed. The method is based on the use of transition count testing. A new formulation of the problem is given in terms of finding a test generator as opposed to solving the problem at the data compaction end. An algorithm is proposed which can be used to find a counter-based test pattern generator. This test generator tests ... View full abstract»

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  • A formal approach to the scheduling problem in high level synthesis

    Publication Year: 1991, Page(s):464 - 475
    Cited by:  Papers (188)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    An integer linear programming (ILP) model for the scheduling problem in high-level synthesis is presented. In addition to time-constrained scheduling and resource-constrained scheduling, a scheduling problem called feasible scheduling, which provides a paradigm for exploring the solution space, is constructed. Extensive consideration is given to the following applications: scheduling with chaining... View full abstract»

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  • A novel critical path heuristic for fast fault grading

    Publication Year: 1991, Page(s):544 - 548
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    A novel fault grading heuristic is presented, based on the critical path tracing technique that tackles the problems associated with fan-out reconverging nodes (FORNs) without using forward propagation of the fault effects. To determine the criticality status of a fan-out reconverging node, which can differ from that of its fan-out branches (FOBs), the concepts of evidencing and masking paths are ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu