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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date Apr 1991

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Displaying Results 1 - 16 of 16
  • DARSI: RC data reduction [VLSI simulation]

    Publication Year: 1991 , Page(s): 493 - 500
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    Taking into account RC effects in VLSI simulation and verification systems, without seriously degrading their efficiency, requires preliminary data reduction. A tool, DARSI (data reduction system for interconnects), that can handle both polysilicon and diffusion resistive effects is presented. It contains the reduction scheme described by S.-L. Su et al. (Proc. IEEE Conf. Computer-Aided Design, p.270-3, 1986), a novel line-based reduction method, a novel loop reduction scheme, and a technique for identifying important diffusion resistors. The number of parasitic elements is considerably reduced, while guaranteeing delay errors to be less than a few percent. DARSI is implemented in a general-purpose rule-based verification environment for VLSI and has a nearly linear complexity. Application to several practical designs is also discussed View full abstract»

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  • Nonlinear transformer model for circuit simulation

    Publication Year: 1991 , Page(s): 476 - 482
    Cited by:  Papers (28)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    A transformer model which consists of a nonlinear core with hysteresis and multiple windings is described as implemented in DSPICE. In contrast to previous implementations, the nonlinear behavior of the new model is described by continuous piecewise-hyperbolic functions characterized by three parameters. These parameters are the same as parameters previously published in the literature. A loop-traversing algorithm has been implemented which avoids discontinuities and eliminates both nonconvergence problems and the occurrence of erroneous voltage spikes during time-domain simulation. In the large-signal time-domain analysis the frequency-dependent eddy current losses in the core and wire losses are modeled. Additional effects, such as wire skin effect and temperature dependence, are also included. In the small-signal AC analysis the transformer is modeled as frequency-dependent lossy mutual inductors. For both analyses, the air gap and the elated fringe field effect are modeled by extending the magnetic path length of the core appropriately View full abstract»

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  • Is redundancy necessary to reduce delay?

    Publication Year: 1991 , Page(s): 427 - 435
    Cited by:  Papers (34)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB)  

    The question of whether single stuck-at-fault redundancies are necessary to increase performance or whether they are only an unnecessary by-product of performance optimization is addressed. A constructive resolution of this question is given in the form of an algorithm that takes as input a combinational circuit and returns an irredundant circuit that is as fast. The utility of this algorithm is demonstrated on a well-known circuit, the carry-skip adder, and a novel irredundant design of that adder is presented. As the algorithm may either increase or decrease circuit area, the authors leave unresolved the question as to whether every circuit has an irredundant circuit that is at least as fast and is of equal or lesser area View full abstract»

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  • An integrated CAD system for algorithm-specific IC design

    Publication Year: 1991 , Page(s): 447 - 463
    Cited by:  Papers (56)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2116 KB)  

    LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described View full abstract»

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  • Numerical analysis of magnetic-field-sensitive bipolar devices

    Publication Year: 1991 , Page(s): 501 - 511
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1044 KB)  

    Two-dimensional numerical solutions to the system of partial differential equations governing galvanomagnetic carrier transport in magnetic-field-sensitive integrated bipolar transistors are presented. The equations are discretized using the finite box procedure with a variation in the standard Scharfetter-Gummel approach adopted for the current continuity equations. High-resolution computations of the potentials in the base region of realistic device structures and operating conditions show that the magnitude of the Hall voltage at the emitter-base junction is too small to cause any appreciable asymmetric minority carrier injection thus invalidating the widely invoked emitter injection modulation model. Measured data obtained using in situ Hall probes are in support of the conclusions derived from the numerical model View full abstract»

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  • A formal approach to the scheduling problem in high level synthesis

    Publication Year: 1991 , Page(s): 464 - 475
    Cited by:  Papers (176)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    An integer linear programming (ILP) model for the scheduling problem in high-level synthesis is presented. In addition to time-constrained scheduling and resource-constrained scheduling, a scheduling problem called feasible scheduling, which provides a paradigm for exploring the solution space, is constructed. Extensive consideration is given to the following applications: scheduling with chaining, multicycle operations by nonpipelined function units, and multicycle operations by pipelined function units; functional pipelining; loop folding; mutually exclusive operations; scheduling under bus constraint; and minimizing lifetimes of variables. The complexity of the number of variables in the formulation is O( s×n) where s and n are the number of control steps and operations, respectively. Since the as soon as possible (ASAP), as late as possible (ALAP), and list scheduling techniques are used to reduce the solution space, the formulation becomes very efficient. A solution to a practical problem, such as the fifth-order filter, can be found optimally in a few seconds View full abstract»

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  • A novel critical path heuristic for fast fault grading

    Publication Year: 1991 , Page(s): 544 - 548
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    A novel fault grading heuristic is presented, based on the critical path tracing technique that tackles the problems associated with fan-out reconverging nodes (FORNs) without using forward propagation of the fault effects. To determine the criticality status of a fan-out reconverging node, which can differ from that of its fan-out branches (FOBs), the concepts of evidencing and masking paths are used. Using the statistics from exact fault simulations, heuristic rules are derived for the generation of masking and evidencing paths. The results obtained on benchmark circuits show good accuracy for fault coverage estimates and a computation time linear in the number of gates and comparable to that of the fault-free simulation View full abstract»

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  • Efficient simulation of MOS circuits

    Publication Year: 1991 , Page(s): 541 - 544
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    Novel techniques are described which significantly speed up classical circuit simulation of MOS LSI circuits. By taking advantage of the unilateral properties of MOS transistors, modifications of Newton's method are developed, reducing the computational effort for the Gaussian elimination mainly for large circuits. Latency is another property of MOS circuits which can be exploited to enhance simulation efficiency. A latency exploitation technique is described. In contrast to methods published previously, no partitioning into subcircuits is required. These techniques can be easily implemented in circuit simulators View full abstract»

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  • A method of reducing aliasing in a built-in self-test environment

    Publication Year: 1991 , Page(s): 548 - 553
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    A method of reducing aliasing in built-in self-test of VLSI circuits is proposed. The method is based on the use of transition count testing. A new formulation of the problem is given in terms of finding a test generator as opposed to solving the problem at the data compaction end. An algorithm is proposed which can be used to find a counter-based test pattern generator. This test generator tests a circuit exhaustively or pseudo-exhaustively so that the aliasing is reduced substantially provided the data compactor used is a transition counter. Experimental results are presented to substantiate these claims View full abstract»

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  • Distributed genetic algorithms for the floorplan design problem

    Publication Year: 1991 , Page(s): 483 - 492
    Cited by:  Papers (44)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB)  

    Designing a VLSI floorplan calls for arranging a given set of modules in the plane to minimize the weighted sum of area and wire-length measures. A method of solving the floorplan design problem using distributed genetic algorithms is presented. Distributed genetic algorithms, based on the paleontological theory of punctuated equilibria, offer a conceptual modification to the traditional genetic algorithms. Experimental results on several problem instances demonstrate the efficacy of this method and indicate the advantages of this method over other methods, such as simulated annealing. The method has performed better than the simulated annealing approach, both in terms of the average cost of the solutions found and the best-found solution, in almost all the problem instances tried View full abstract»

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  • Multilevel logic synthesis of symmetric switching functions

    Publication Year: 1991 , Page(s): 436 - 446
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB)  

    Designs of totally symmetric functions provided by logic synthesis systems have on average more than twice as many literals as best designs, while the designs of nonsymmetric functions have on average 20% more literals. A simple, but effective, heuristic method for synthesizing symmetric functions that detects and takes advantage of symmetry and is based on classic disjoint decomposition theory is fully developed from basic definitions. Functions are realized as Boolean networks with cost measured as the literal count of factored expressions. Programs based on the method almost always produce the best designs known to the authors. Two strategies for accepting decompositions are explored. They do produce different results in a few cases: examples are presented to show that neither always produces best designs. These programs are proposed as preprocessors for a comprehensive synthesis system View full abstract»

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  • Combinatorial optimization by stochastic evolution

    Publication Year: 1991 , Page(s): 525 - 535
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1032 KB)  

    A novel technique is introduced, called stochastic evolution (SE), for solving a wide range of combinatorial optimization problems. It is shown that SE can be specifically tailored to solve the network bisection, traveling salesman, and standard cell placement problems. Experimental results for these problems show that SE can produce better quality solutions than sophisticated simulated annealing (SA)-based heuristics in a much shorter computation time View full abstract»

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  • A tool for hierarchical test generation

    Publication Year: 1991 , Page(s): 519 - 524
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    An extended system MSST (MIMOLA software system test generator), and its algorithms for automatic test generation are presented. In a hierarchical, mixed-level approach (from gate to system level) test patterns for sequential circuits and test programs for external testing or self-testing (diagnostics) of microprocessor boards or processor systems can be generated automatically. In a complete hierarchy lower bounds for test coverage are easily computable. The MIMOLA design system (including MSST) has been installed on VAX, APOLLO, SUN, and several other host machines. Several production line test applications show good results View full abstract»

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  • Reduced offsets for minimization of binary-valued functions

    Publication Year: 1991 , Page(s): 413 - 426
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1148 KB)  

    A modified approach to two-level logic minimization is described which obviates the need to compute the offset, yet provides the same global picture available with the offset. This approach is based on a new concept called the reduced offset. It is shown that reduced offsets can be computed without using the offset. This scheme has been implemented in ESPRESSO with an interface to the multilevel minimization environment MIS, where it is used to minimize individual nodes (representing two-level functions with single outputs) in multilevel networks. Such functions usually have very large offsets because of a large number of variables in their don't care sets. The modified approach is up to 8.5 times faster than ESPRESSO on a set of benchmark examples View full abstract»

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  • N-channel MOSFET model for the 60-300-K temperature range

    Publication Year: 1991 , Page(s): 512 - 518
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    An engineering model of the short-channel NMOS transistor which is applicable to both room-temperature and cryogenic device operation is presented. The model incorporates the nonuniversal dependence of the effective channel mobility on the effective vertical field, which is ignored in room-temperature device models. Described also is a novel method to account for the bulk charge effect in the presence of drift velocity saturation, channel length modulation, charge sharing by the drain and source, and temperature dependence of the critical field. The proposed model is verified by comparison with experimental device characteristics obtained over a wide range of terminal voltages, temperatures, and channel lengths View full abstract»

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  • A layout modification approach to via minimization

    Publication Year: 1991 , Page(s): 536 - 541
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    The approach is to eliminate vias systematically by modifying the routing layout. The algorithm was implemented and applied to benchmark routing layouts published in the literature. Significant reduction in the number of vias was obtained without increasing the routing area. The experimental results show that the algorithm is more effective in via reduction and more efficient in running time than conventional via minimization algorithms. In particular, for Burstein's 19-track two-layer routing solution to Deutsch's difficult problem, the algorithm obtains a 34% reduction in the number of vias, which is more than an 11% improvement over the conventional constrained via minimization (CVM) approach. The application of the algorithm to various solutions to Deutsch's difficult problem produces the fewest of vias ever reported in the literature View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu