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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Apr 1991

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Displaying Results 1 - 25 of 37
  • Multiemitter BiCMOS logic circuit family

    Publication Year: 1991 , Page(s): 665 - 669
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    A new multiemitter BiCMOS circuit using half-micrometer BiCMOS technology with a 3.6-V supply provides 85 % improvement in delay over CMOS design and 40 % improvement over conventional BiCMOS. This benefit is demonstrated in a 64-b carry look-ahead adder where most of the gates have a high number of inputs. A complete logic circuit family based on the multiemitter (ME) concept is proposed in a gate-array structure View full abstract»

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  • 100-MHz serial access architecture for 4-Mb field memory

    Publication Year: 1991 , Page(s): 555 - 559
    Cited by:  Papers (1)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A 4-Mb field memory with a 100-MHz serial access rate has been developed. A new architecture that significantly improves serial I/O operation speed, reduces layout area, and offers simple control is proposed. To accomplish this task, a new architectural data shifter and high-speed redundancy circuit have been developed. The field memory has a 568-line×960 pixel×8-b (4,362,240 b) memory cell array designed for high-definition television (HDTV) screens. A 1.0 μm CMOS process technology is used to produce a die size of 12.94 mm×25.9 mm. The write-read cycle time is 9 ns, the access time is 8 ns, and the active current is 170 mA at a 50-MHz cycle rate with a standby current of about 3 mA View full abstract»

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  • A 10 ns 54×54 b parallel structured full array multiplier with 0.5 μm CMOS technology

    Publication Year: 1991 , Page(s): 600 - 606
    Cited by:  Papers (60)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    A 54 b×54 b multiplier fabricated in a double-metal 0.5 μm CMOS technology is described. The 54 b×54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz View full abstract»

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  • A circuit design of intelligent cache DRAM with automatic write-back capability

    Publication Year: 1991 , Page(s): 560 - 565
    Cited by:  Papers (3)  |  Patents (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    An intelligent cache based on a distributed architecture that consists of a hierarchy of three memory sections-DRAM (dynamic RAM), SRAM (static RAM), and CAM (content addressable memory) as an on-chip tag-is reported. The test device of the memory core is fabricated in a 0.6 μm double-metal CMOS standard DRAM process, and the CAM matrix and control logic are embedded in the array. The array architecture can be applied to 16-Mb DRAM with less than 12% of the chip overhead. In addition to the tag, the array embedded CAM matrix supports a write-back function that provides a short read/write cycle time. The cache DRAM also has pin compatibility with address nonmultiplexed memories. By achieving a reasonable hit ratio (90%), this cache DRAM provides a high-performance intelligent main memory with a 12 ns(hit)/34 ns(average) cycle time and 55 mA (at 25 MHz) operating current View full abstract»

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  • A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

    Publication Year: 1991 , Page(s): 507 - 512
    Cited by:  Papers (11)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 μm BiCMOS process. An improved buffer with a high-level output of nearly VCC is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the ×1 output, having the same critical path as the ×4 output circuit, allows for the same access time between the two modes. The ×1 or ×4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the × mode View full abstract»

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  • A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

    Publication Year: 1991 , Page(s): 607 - 611
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    A learning neural network LSI chip is described. The chip integrates 125 neuron units and 10K synapse units with the 1.0 μm double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by using a mixed design architecture of digital and analog circuits. The fully feedback connection network LSI can memorize at least 15 patterns with 50 μs learning time for each pattern. Under the condition that each test vector keeps a Hamming distance of 6 from memorized pattern, a correct association rate of 98% is obtained. The relaxation time is 1 to 2 μs. This chip consumes less than 7.5 W View full abstract»

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  • Josephson macrocell array

    Publication Year: 1991 , Page(s): 612 - 617
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    A modified variable-threshold logic (MVTL) gate for use in Josephson LSI circuits is considered. A 7.6 K-gate Josephison macrocell array whose functions can be changed by wiring changing has been developed. Automatic design problems, such as AC powering and small fan-outs, are solved by constructing the macrocell with a three-phase powering system and developing a magnetically coupled unit cell. The chip contains 21440 Josephson junctions on a 5 mm×5 mm die and is fabricated using 1.5 μm all-niobium Josephson techniques. An average delay of 5.3 ps/gate in the macrocell and a total chip power consumption of 23 mW have been obtained View full abstract»

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  • An 8 ns 4 Mb serial access memory

    Publication Year: 1991 , Page(s): 502 - 506
    Cited by:  Papers (3)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V View full abstract»

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  • A high-speed low-power JFET pull-down ECL circuit

    Publication Year: 1991 , Page(s): 679 - 683
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    An active pull-down output stage that utilizes a composite junction FET (JFET), applied in a high-speed low-power emitter-coupled logic (ECL) circuit, is described. The composite JFET structure is produced by modifying the existing bipolar transistor layout so that a p-channel JFET is formed next to an n-p-n transistor without need of any extra process steps. This p-channel JFET is a four-terminal device: the intrinsic base region defines the channel, the two separate extrinsic bases become the source and drain, the emitter region is the primary gate, and the collector is used as the back gate. The JFET has the same doping profile as the n-p-n bipolar transistor in the intrinsic device region. Simulation results based on a 0.8-μm double poly-Si, self-aligned bipolar technology indicate that the circuit with a typical loading at a power consumption of 1 mW per gate offers a 24% improvement in the pull-down delay and a 53% improvement in the load driving capability compared with the conventional ECL circuit View full abstract»

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  • Design of a second-level cache chip for shared-bus multimicroprocessor systems

    Publication Year: 1991 , Page(s): 566 - 571
    Cited by:  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 μm CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic View full abstract»

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  • Full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration

    Publication Year: 1991 , Page(s): 578 - 584
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    Various full-swing BiCMOS logic circuits with complementary emitter-follower driver configurations are described. The performance of the circuits is demonstrated in a 1.2 μm complementary BiCMOS technology with a 6 GHz n-p-n and a 2 GHz p-n-p transistor. For the basic circuit, gate delay (fan-in=2, fan-out=1) is 366 ps and driving capability is 288 ps/pF at 4 V. Delay-power tradeoffs that depend on characteristics of the clamping diode between two base nodes of the complementary emitter-follower driver, parasitic capacitances at the two base nodes, and a technique that can be used to achieve full swing have been identified for these circuits. These circuits show leverage over the conventional BiCMOS circuit for reduced power-supply voltages View full abstract»

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  • A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS

    Publication Year: 1991 , Page(s): 628 - 636
    Cited by:  Papers (121)  |  Patents (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (828 KB)  

    Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3-μm CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil2 (26 mm2), with a single 5-V supply and two-phase nonoverlapping clock View full abstract»

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  • Analysis and optimization of BiCMOS digital circuit structures

    Publication Year: 1991 , Page(s): 676 - 679
    Cited by:  Papers (15)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    Circuit analyses and performance optimization are presented of three basic BiCMOS digital circuit structures: BiCMOS buffer, NMOS/CML (coupled-mode logic), and ECL (emitter-coupled logic)/CMOS interface circuits. The analytical modeling of the transient behavior offers insight into the critical circuit and device parameters that affect the performance of these circuits. Techniques to improve the speed of each structure and the tradeoff factors involved in designing such circuits are discussed. The derived delay expressions can also be used in CAD tools for optimizing BiCMOS circuits and systems View full abstract»

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  • A highly sensitive on-chip charge detector for CCD area image sensor

    Publication Year: 1991 , Page(s): 652 - 656
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    A novel on-chip charge detector for charge-coupled-device (CCD) image sensor applications was fabricated and evaluated. The device, called the double-gate floating surface detector, achieves a charge/voltage conversion gain of 220 μV/electron, a noise equivalent electron of 0.5 electrons r.m.s. and a dynamic range of 79 dB over 3.58-MHz video bandwidth at room temperature. In the small-signal region under 20 electrons, which is the photon counting region for highly sensitive imaging devices, the device was evaluated by observing the discrete voltage levels corresponding to the number of signal electrons on an oscilloscope. This evaluation confirmed that the high charge voltage conversion gain is also maintained in this region View full abstract»

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  • A divided/shared bit-line sensing scheme for ULSI DRAM cores

    Publication Year: 1991 , Page(s): 473 - 478
    Cited by:  Papers (3)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly View full abstract»

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  • PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

    Publication Year: 1991 , Page(s): 585 - 589
    Cited by:  Papers (18)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 μm BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz View full abstract»

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  • NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit

    Publication Year: 1991 , Page(s): 661 - 665
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A high-speed low-power nonthreshold-logic (NTL)-based push-pull logic circuit, featuring a complementary emitter-follower driver is presented. Compared with the standard NTL circuit, the circuit offers a much better balance between the pull-up and pull-down delay, improved scalability, and superior load driving capability. Simulation results based on a 0.8-μm double-poly. self-aligned complementary bipolar technology indicate that at a power consumption of 1.22 mW/gate, the circuit offers 2.4× improvement in the pull-down delay of a loaded gate and 4.0× improvement in the load driving capability over the standard NTL circuit. The design and scaling considerations of the circuit are discussed View full abstract»

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  • Fast-access BiCMOS SRAM architecture with a VSS generator

    Publication Year: 1991 , Page(s): 513 - 517
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with VSS generator has been developed. Two key circuits, a VSS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described View full abstract»

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  • 100-MHz monolithic low-pass filters with transmission zeros using NIC integrators

    Publication Year: 1991 , Page(s): 669 - 671
    Cited by:  Papers (13)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    A monolithic method of implementing VHF filters with transmission zeros is presented. The transmission zeros are obtained using a modified leapfrog simulation method realized without floating capacitors that does not require summing circuits inside the feedback loops. The integrators used are balanced negative impedance converter (NIC) integrators with grounded capacitors, which do not require p-n-p transistors and are suited for low-voltage applications. A low-pass filter with a cutoff frequency of 100 MHz and with a transmission zero at 166 MHz designed and built in an integrated circuit form showed good results, confirming the feasibility of the method View full abstract»

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  • Pipelined, time-sharing access technique for an integrated multiport memory

    Publication Year: 1991 , Page(s): 549 - 554
    Cited by:  Papers (14)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    A pipelined, time-sharing access (PTA) technique that realizes an integrated multiport memory for high-speed signal processing is described. N/2-port memory cells, with less area and a wider operating margin, are used for the N-port memory function. Memory cell access for multiple ports is performed serially within one cycle, instead of being an ordinary parallel operation. Memory operation is divided into three pipeline cycles-address selection, memory cell access, and data I/O operation-to reduce the cycle time. A 64-kb four-port memory was fabricated with conventional two-port memory cells to verify the effectiveness of this technique. A 16 ns memory operation with a wide margin was observed under a 3 V supply voltage View full abstract»

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  • A high-speed sample-and-hold technique using a Miller hold capacitance

    Publication Year: 1991 , Page(s): 643 - 651
    Cited by:  Papers (36)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB)  

    A circuit technique is introduced for increasing the precision of an open-loop sample-and-hold circuit without significantly reducing the sampling speed. With this technique, the sampling error resulting from input-dependent charge injection of the sampling switch is significantly attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is, in effect, increased during the transition to the hold mode through the action of Miller feedback. The technique thus allows for a high sampling speed without the precision penalty traditionally associated with open-loop sample-and-hold circuits. A sample-and-hold circuit based on the proposed approach has been designed and fabricated in a 1-μm CMOS technology, and an order-of-magnitude of reduction in the input-dependent charge injection has been demonstrated experimentally. This prototype circuit is capable of sampling an input to a precision of 8 b with an acquisition time of 5 ns. The experimental sample-and-hold circuit operates from a single 5-V supply and dissipates 26.5 mW View full abstract»

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  • A dynamic three-state memory cell for high-density associative processors

    Publication Year: 1991 , Page(s): 537 - 541
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    A dynamic associative processor cell is described. The cell stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two overlapping dual-gate structures available in MIT's CCD/CMOS technology. Dual-gate CCD transistors are used to reduce the charge-spooning current, which can discharge the storage node through the write transistors. The use of the cell in an associative processor is described, and experimental results are presented View full abstract»

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  • Digitally programmable gain control circuit for charge-domain signal processing

    Publication Year: 1991 , Page(s): 683 - 686
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    A simple, nearly passive circuit for programmable gain control of charge-domain signals is described. The circuit is functionally equivalent to a multiplying digital-to-analog converter (MDAC) and is implemented in a 3-μm double-poly, double-metal charge-coupled device (CCD) process. Two implementations of the circuit are reported: a single-stage recursive converter, and a ten-stage pipeline converter. The latter occupies 0.4 mm2 of chip area and consumes approximately 2 μW for a 1-kHz conversion rate. The circuit is shown experimentally to have all 8-b equivalent accuracy in both differential and integral linearity and is expected to find application in focal-plane image processing for both detector nonuniformity correction and convolution weighting View full abstract»

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  • A high-speed clamped bit-line current-mode sense amplifier

    Publication Year: 1991 , Page(s): 542 - 548
    Cited by:  Papers (53)  |  Patents (113)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling View full abstract»

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  • A 1 Mb EEPROM with MONOS memory cell for semiconductor disk application

    Publication Year: 1991 , Page(s): 497 - 501
    Cited by:  Papers (9)  |  Patents (272)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    A 1 Mb 5 V-only EEPROM (electrically erasable programmable ROM) with metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells specifically designed for a semiconductor disk application is described. The memory has high endurance to write/erase cycles and a relatively low programming voltage of ±9 V. These advantages result from the structure and the characteristics of the MONOS memory cell. A newly developed dual-gate-type MONOS memory cell has a small unit cell area of 18.4 μm2 with 1.2 μm lithography, and the die size of the fabricated chip is 5.3 mm×6.3 mm. A new programming scheme called multiblock erase solved the problem of slow programming speed. A programming speed of up to 1.1 μs/B equivalent (140 ms/chip) was obtained View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan