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Solid-State Circuits, IEEE Journal of

Issue 3 • Date March 1991

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Displaying Results 1 - 25 of 37
  • A self-testing reconfigurable CAM

    Publication Year: 1991 , Page(s): 257 - 261
    Cited by:  Papers (17)  |  Patents (42)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    The authors describe a 2- mu m CMOS reconfigurable content addressable memory (RCAM), organized as 256 words by 64 b, that can be written, searched, or read with 100-ns cycle time. Designed for general high-speed table lookup applications, the RCAM has self-test and reconfiguration features to simplify testing and improve yield. In test mode the RCAM tests the whole memory array in under 300 clock cycles and automatically reconfigures itself to correct any hard errors it finds, greatly enhancing the chip yield. As an example, the authors describe the application of the RCAM to address translation. Compared to RAM-based address translation, using the RCAM increases speed and reduces complexity. Also, the RCAM's storage reclamation feature simplifies system storage management by allowing old entries that have not been accessed recently to be freed for reuse.<> View full abstract»

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  • SILAS: a knowledge-based simulation assistant

    Publication Year: 1991 , Page(s): 310 - 318
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1020 KB)  

    A knowledge-based shell for circuit simulation has been developed as a part of a design environment for analog circuits. This shell offers circuit-specific simulation support exploiting expert knowledge for dealing with problems like test function generation and simulation clustering. Furthermore, it provides worst-case analysis capabilities as well as automatic documentation facilities like data sheet generation and a design database. The prototype implementation, SILAS, has been realized as an expert system with blackboard architecture. Knowledge and knowledge execution are strictly separated to allow an easy extension of the incorporated knowledge bases. SILAS is organized as a simulation assistant, which means the user may specify a specific task by a work plan while the task organization and control are taken over by the system. Application areas are all domains which require automated circuit characterization such as synthesis or cell library maintenance View full abstract»

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  • Design of reliable VLSI circuits using simulation techniques

    Publication Year: 1991 , Page(s): 452 - 457
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    An iterative simulation method of predicting the impact of progressive device degradation on circuit performance due to common microelectronic failure mechanisms is described. Simulation schemes for the lifetime prediction of ASICs as well as modeling requirements for accurate and efficient simulation are presented. These simulation schemes have been implemented in the prototype reliability simulator RELY to evaluate circuit performance degradation and provide reliability enhancement information. Hot-carrier effects on submicrometer digital and analog circuits are used to demonstrate the approach. Experimental results on precharging circuitry for sense amplifiers and operational amplifiers are presented View full abstract»

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  • A 0.8-μm advanced single-poly BiCMOS technology for high-density and high-performance applications

    Publication Year: 1991 , Page(s): 422 - 426
    Cited by:  Papers (10)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    A single-poly, 0.8-μm advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process View full abstract»

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  • A technology-independent approach to custom analog cell generation

    Publication Year: 1991 , Page(s): 386 - 393
    Cited by:  Papers (25)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    STAT (schematic to artwork transistor), a set of software tools designed to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology, is described. The system enables the circuit designer to annotate the schematic with component matching and symmetry relationships. Software subroutines are then used to generate device artwork. The placement program implements algorithms in which groups of related components are placed first so that annotated layout constraints are preserved. A novel placement method is offered which recognizes that analog schematic topologies often reflect desirable layout configurations. A flexible multilayer cell-level router has been developed to complete the device interconnection. The STAT system functions in either a polygon or symbolic layout environment. The symbolic layout allows design-rule and technology changes to be made easily and is designed to interface with a commercial compaction program to produce the final layout View full abstract»

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  • A bipolar-PMOS merged basic cell for 0.8 μm BiCMOS sea of gates

    Publication Year: 1991 , Page(s): 427 - 431
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A compact basic cell for BiCMOS sea-of-gates (SOG) circuits was developed using a bipolar-PMOS merged structure and gate-isolated bipolar transistors. The new cell structure reduces the cell area using the bipolar-PMOS merged transistors. The cell has no restrictions regarding macrocell placement because it has no shared element. The cell density is 60% higher than that of conventional cells. Three types of circuits are provided for a macrocell using the basic cell. The pull-up BiCMOS circuit, one of the circuit alternatives, obtains the shortest gate delay with average load capacitance and high density comparable to a pure CMOS density. The gate delay of 200 ps was achieved with the pull-up BiCMOS two-input NAND gate fabricated with 0.8-μm BiCMOS technology View full abstract»

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  • A 6-ns 256-kb BiCMOS TTL SRAM

    Publication Year: 1991 , Page(s): 439 - 443
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25°C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8-μm Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a ×8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm×10 mm View full abstract»

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  • Two-level pipelined systolic array graphics engine

    Publication Year: 1991 , Page(s): 229 - 236
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-μm CMOS technology View full abstract»

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  • SYMCELL-a symbolic standard cell system

    Publication Year: 1991 , Page(s): 449 - 452
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    A SYMCELL system is used to create research VLSI prototypes because it permits rapid realization of reasonably high-performance chips. The SYMCELL process flow consists of library creation; schematic capture and logic simulation; netlist translation; layout planning (cell placement and global routing); layout implementation (cell gridding and fine routing); layout verification and simulation; and chip assembly. SYMCELL is a standard cell system that enables cells to be created, placed, and globally routed symbolically. After this symbolic realization, cell rows are compacted and pitch-matched and channels are routed for a specific set of layout rules. The symbolic cell libraries can be maintained independently of the process layout rules, and new cells can be created with the ease of symbolic layout. The system is especially useful in research because of the ease with which the cell library can be mapped to new sets of layout rules View full abstract»

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  • A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency

    Publication Year: 1991 , Page(s): 435 - 439
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    A digital interpolation filter chip with 32 programmable coefficients designed for baseband pulse shaping in digital microwave radio modems is presented. The chip was designed for a maximum sampling frequency of 80 MHz, under worst-case conditions. The desired throughput rate is achieved by applying a pipelined carry-save arithmetic. Although an optimized pipeline scheme was used, the chip complexity leads to a high capacitive clock load. The synchronization problems and the switching noise problems resulting from this high clock load were solved by dividing the clock system into subsystems and introducing and intended clock skew between the subsystems and by applying a power supply concept in which the global supply lines are consistently routed in a sandwich structure to create an on-chip buffer capacitance. The chip contains 160000 transistors on a silicon area of 78 mm2. Typical samples were tested, and although they were fabricated in a moderate 1.5-μm CMOS technology, their full logical functionality was verified for sampling frequencies of up to 220 MHz View full abstract»

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  • High-density central I/O circuits for CMOS

    Publication Year: 1991 , Page(s): 431 - 435
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    An I/O circuit design for VLSI CMOS is described that reduced the percentage of chip area occupied by I/O circuits from roughly 22% to under 3% for a 256 I/O chip. The technique, implemented in the IBM RISC System/6000 workstation processor chips, uses stackable macros to improve density per I/O signal by 10 times. The reorganization of the I/O structure relies on a top layer of metal dedicated to I/O circuit-to-pad wiring and power distribution. It takes full advantage of C4 solder bond package connection technology, which allows package connections to be located over chip circuitry. Decoupling I/O circuit layout from package connection layout and grouping by identical circuit type permits the full range of layout optimization techniques to be applied. I/O circuits are produced that are fully compatible with internal circuit terrain View full abstract»

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  • Circuit partitioning for logic synthesis

    Publication Year: 1991 , Page(s): 350 - 363
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1308 KB)  

    The authors introduce a circuit partitioning method based on analysis of reconvergent fan-out. A corolla is defined as a set of overlapping reconvergent fan-out regions. The authors partition the circuit into a set of disjoint corollas and use the corollas to resynthesize the circuit. The authors develop the notion of resynthesis potential of a logic circuit and use it to select corollas that resynthesize with most gain. It is shown that resynthesis of large benchmark circuits using the corollas consistently reduces transistor pairs and layout area while improving delay and testability. The use of don't cares to further minimize the corollas in the local context and the global context is explored View full abstract»

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  • A VLSI grammar processing subsystem for a real-time large-vocabulary continuous speech recognition system

    Publication Year: 1991 , Page(s): 443 - 448
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    The architecture and custom implementation of a grammar processing subsystem for a real-time large-vocabulary continuous speech recognition system using hidden Markov models are described. The prototype has 3000, words and larger vocabularies and higher throughput can be obtained by adding more grammar processors. This subsystem contains two custom VLSI chips that perform the evaluation of starting word probabilities associated with the across-word transitions in the hidden-Markov-model (HMM)-based speech recognition system. This system has a maximum computation rate of 200 MOPS and an I/O bandwidth of 265 MB/s. All circuits were silicon compiled and were working on first silicon View full abstract»

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  • A chip set for lossless image compression

    Publication Year: 1991 , Page(s): 237 - 244
    Cited by:  Papers (9)  |  Patents (53)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    The authors describe two chips which form the basis of a high-speed lossless image compression/decompression system. They present the transform and coding algorithms and the main architectural features of the chips and outline some performance specifications. Lossless compression can be achieved by a transformation process followed by entropy coding. The two application-specific integrated circuits (ASICs) perform S-transform image decomposition and the Lempel-Ziv (L-Z) type of entropy coding. The S-transform, besides decorrelating the image, provides a convenient method of hierarchical image decomposition. The data compressor/decompressor IC is a fast and efficient implementation of the L-Z algorithm. The chips can be used independently or together for image compression View full abstract»

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  • Flexibility of interconnection structures for field-programmable gate arrays

    Publication Year: 1991 , Page(s): 277 - 282
    Cited by:  Papers (98)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility View full abstract»

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  • A flexible multiport RAM compiler for data path

    Publication Year: 1991 , Page(s): 343 - 349
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both layout and port organization. Fast access time and fully static and asynchronous port operation are also goals. A wide bit-word organization range including 16 b×2048 words and 72 b×512 words was also obtained. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no DC power consumption. The address access times of the generated three-port RAMs are, for example, 5.0 ns for 1 K and 11.0 ns for 32 K View full abstract»

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  • AlInAs/GaInAs HBT IC technology

    Publication Year: 1991 , Page(s): 415 - 421
    Cited by:  Papers (27)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    Integrated circuits (ICs) fabricated with AlGaAs/GaInAs heterojunction bipolar transistors (HBTs) lattice matched to InP substrates are described. The transistors used in this work consisted of an abrupt emitter-base junction design. A cutoff frequency and a maximum frequency of oscillation of 90 and 70 GHz, respectively, have been achieved with a 2×5-μm2 emitter size HBT. Current-mode logic (CML) was used to demonstrate ring oscillators, flip-flop divider circuits, and dual-modulus prescalers. The ring oscillator demonstrated a 15.8-ps gate delay, the CML flip-flop divider circuits demonstrated 24.8-GHz toggle rates, and the 4/5 and 8/9 dual-modulus prescalers consisting of 106 and 124 transistors, respectively, operated at clock rates of up to 9 GHz View full abstract»

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  • A behavioral model of A/D converters using a mixed-mode simulator

    Publication Year: 1991 , Page(s): 283 - 290
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    A mixed-mode behavioral model of analog-to-digital (A/D) converters is described. A generalized model structure is introduced. The basic function of an A/D converter is to convert an analog voltage into a digital code, for example, a binary number. Three conversion methods (successive approximation, flash, and dual integration) which are commonly used in A/D converters are modeled and can be selected simply by specifying a parameter of the model. For brevity, only the successive-approximation method is described. The modeling considerations of various parts in the A/D converter, including the input amplifier, D/A converter, comparator, and the synchronization problem, are described. The model has been implemented in the Saber mixed-mode simulator. Simulation results are given View full abstract»

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  • Hierarchical symbolic design methodology for large-scale data paths

    Publication Year: 1991 , Page(s): 381 - 385
    Cited by:  Papers (3)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21 K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design View full abstract»

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  • A high-frequency fully differential BiCMOS operational amplifier

    Publication Year: 1991 , Page(s): 203 - 208
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages View full abstract»

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  • Automatic verification of library-based IC designs

    Publication Year: 1991 , Page(s): 394 - 403
    Cited by:  Papers (9)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    A new method is presented for fully automatic verification of layout, generated with a library-based IC design system. The method overcomes the limitation of traditional simulation-based verification techniques. It is based on a stepwise bottom-up reconstruction of large architecture building blocks, starting from the layout. Using a pattern matcher, the simplest cells in the transistor netlist, such as inverters, NAND gates, etc., are identified first. Then the pattern matcher is used again to find the next level of cells, such as memory cells, flip-flops, etc. Reconstruction of more and more complex structures takes place, until the architecture level is reached. To be able to communicate instances of parametrized library modules, the parameters have to define the module's connectivity in a unique way. For every module, a controller can then be established which guides the reconstruction process. When the design is correct, the reconstruction will succeed. On the other hand, if at some point the reconstruction fails, this indicates incorrect connectivity at that point View full abstract»

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  • KOAN/ANAGRAM II: new tools for device-level analog placement and routing

    Publication Year: 1991 , Page(s): 330 - 342
    Cited by:  Papers (143)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1628 KB)  

    The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented View full abstract»

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  • Logic synthesis of race-free asynchronous CMOS circuits

    Publication Year: 1991 , Page(s): 371 - 380
    Cited by:  Papers (20)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    A synthesis method for generating race-free asynchronous CMOS circuits that are independent of the internal and output delays is presented. The design method is based on the properties of the negative gates. An inertial delay is associated with each negative gate in a CMOS circuit. Such a gate model is quite realistic. The basic principle of the method presented is to augment and to modify the original flow table in such a way that the obtained logic diagram contains only negative gates. In addition, the synthesis method is capable of avoiding any race, and consequently any critical race or hazard. The method minimizes the number of internal variables and therefore the number of gates, providing new simple cells for fast and low-power integrated circuits View full abstract»

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  • A 66-MHz DSP-augmented RAMDAC for smooth-shaded graphic applications

    Publication Year: 1991 , Page(s): 217 - 228
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1132 KB)  

    A fundamentally new type of RAMDAC is described in which a custom digital signal processor (DSP) is interposed between the RAM and the DAC. The device provides pseudoincreased resolution and increased color range by means of real-time mixing of any two colors contained in the color palette. This feature allows color images to be displayed without the familiar jagged edges; the ability to represent continuous edges yields the name continuous edge graphics (CEG) RAMDAC. Instead of all pixel values representing pointers to colors, 32 now represent a ratio between colors. The device allows mixing between any of the remaining 223 colors in amounts that depend on which ratio is used. This drastically increases the number of colors that an 8-b frame buffer can represent from 256 to over 700000. The device, containing 60000 devices, is fabricated in a 1.2-μm CMOS process supporting a 15-ns cycle operation View full abstract»

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  • A general-purpose high-speed equalizer

    Publication Year: 1991 , Page(s): 209 - 216
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and high-definition multiplexed analog components (HD-MAC) transmission standards. The circuit is a self-adaptive 16-tap transversal filter achieving equalization on any 8-b coded signal. It contains periodically a window of binary or duobinary data samples, such as the D, D2, and HD-MAC signals. This chip includes a delay line of 240 8-b data samples which are used for the internal gradient computations. Only linear distortions (echos) can be corrected by this chip. This 105000-transistor chip has been designed in a CMOS 1.0-μm technology and is being used in a D2-MAC reception environment View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan