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Computers, IEEE Transactions on

Issue 2 • Date Feb. 1991

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Displaying Results 1 - 14 of 14
  • Square meshes are not always optimal

    Publication Year: 1991 , Page(s): 196 - 204
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (759 KB)  

    Mesh-connected computers with multiple buses providing broadcast facilities along rows and columns are discussed. A tight bound of Theta (n/sup 1/8/) is established for the number of rounds required for semigroup computations on n values distributed on a two-dimensional rectangular mesh of size n with a bus on every row and column. The upper bound is obtained for a skewed rectangular mesh of dimensions n/sup 3/8/*n/sup 5/8/. This result is compared to the tight bound of Theta (n/sup 1/6/) for the same problem on the square (n/sup 1/2/*n/sup 1/2/) mesh. It is shown that in the presence of multiple buses, a skewed configuration may perform better than a square configuration for certain computational tasks. The result can be extended to the d-dimensional mesh, giving a lower bound of Omega (n/sup 1/d alpha /) and an upper bound of O(d2/sup d+1/ n/sup 1/d alpha /), where alpha =2/sup d/; these bounds are optimal within constant factors for any constant d. It is noted that for d>3, the results of are mostly of theoretical interest.<> View full abstract»

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  • Increased throughput for the testing and repair of RAMs with redundancy

    Publication Year: 1991 , Page(s): 154 - 166
    Cited by:  Papers (33)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB)  

    The problem of determining whether a redundant random-access memory (RRAM) containing faulty memory cells can be repaired with spare rows and columns is discussed. The approach is to increase the number of working RRAMs manufactured per unit time, rather than per wafer, by presenting a computationally efficient algorithm for detecting unrepairability, a computationally efficient algorithm for optimal repair for special patterns of faulty memory cells and online algorithms that can find an optimal repair or else detect unrepairability during memory testing, aborting unnecessary testing. Experimental validation of the approach is given that is based on industrial device fabrication data View full abstract»

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  • Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding

    Publication Year: 1991 , Page(s): 178 - 195
    Cited by:  Papers (150)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1556 KB)  

    Rate-optimal compile-time multiprocessor scheduling of iterative dataflow programs suitable for real-time signal processing applications is discussed. It is shown that recursions or loops in the programs lead to an inherent lower bound on the achievable iteration period, referred to as the iteration bound. A multiprocessor schedule is rate-optimal if the iteration period equals the iteration bound. Systematic unfolding of iterative dataflow programs is proposed, and properties of unfolded dataflow programs are studied. Unfolding increases the number of tasks in a program, unravels the hidden concurrently in iterative dataflow programs, and can reduce the iteration period. A special class of iterative dataflow programs, referred to as perfect-rate programs, is introduced. Each loop in these programs has a single register. Perfect-rate programs can always be scheduled rate optimally (requiring no retiming or unfolding transformation). It is also shown that unfolding any program by an optimum unfolding factor transforms any arbitrary program to an equivalent perfect-rate program, which can then be scheduled rate optimally. This optimum unfolding factor for any arbitrary program is the least common multiple of the number of registers (or delays) in all loops and is independent of the node execution times. An upper bound on the number of processors for rate-optimal scheduling is given View full abstract»

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  • A parallel time/hardware tradeoff T.H=O(2n/2 ) for the knapsack problem

    Publication Year: 1991 , Page(s): 221 - 225
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    A parallel algorithm for solving the knapsack problem on a single-instruction, multiple-data machine with shared memory is presented. The shared memory allows concurrent reading while concurrent writing is forbidden. The knapsack problem is of size n, which the algorithm solves in time T=O(n×(2 n/2)ε) when P=O((2n/2 )(1-ε)), 0⩽ε⩽1, processors are available. It is shown that the algorithm needs S=O(2 n/2) memory space in a shared memory. If H (for hardware) is the number of processors plus the number of memory cells used by a parallel algorithm, the parallel algorithm takes a linear time proportional to (n/2) to find a solution when P=O (2n/2), leading a tradeoff T×H= O(2n/2) View full abstract»

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  • A study of odd graphs as fault-tolerant interconnection networks

    Publication Year: 1991 , Page(s): 225 - 232
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    Odd graphs are analyzed to determine their suitable in designing interconnection networks. These networks are shown to possess many features that make them competitive with other architectures, such as ring, star, mesh, the binary n-cube and its generalized form, the chordal ring, and flip-trees. Among the features are small internode distances, a lighter density, simplicity in implementing various self-routing algorithms (both for faulty and nonfaulty networks), capability of maximal fault tolerance, strong resilience, and good persistence. The routing algorithms (both for the faulty and fault-free networks) do not require any table lookup mechanism, and intermediate nodes do not need to modify the message. These graphs are shown to have a partitioning property that is based on Hadamard matrices and can be effectively used for a system's expansion and self-diagnostics View full abstract»

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  • Improved diagnosability algorithms

    Publication Year: 1991 , Page(s): 143 - 153
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    The concepts of the PMC and BGM self-diagnosing system models of F. P. Preparata et al. (1967) and F. Barsi et al. (1976), respectively, including the notions of fault sets, consistency, and diagnosability number, are reviewed. Two one-step diagnosability algorithms are applied, one to the PMC model and the other to the BGM model. In both models, one-step diagnosability refers to a system's ability to determine all the faulty units from single collection of test results. Using the letters n, m, and τ to denote the number of units, the number of tests, and the diagnosability number, respectively, it is shown that in the BGM model the algorithm has a complexity of O(nτ2/log τ), and, in the PMC model, the algorithm has a complexity of O(nτ2.5) View full abstract»

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  • Minimization algorithms for multiple-valued programmable logic arrays

    Publication Year: 1991 , Page(s): 167 - 177
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    The performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the charge-coupled device (CCD) and CMOS programmable logic arrays (PLAs) of H.G. Kerkhoff and J.T. Butler (1986) and J.G. Samson (1988), respectively, is analyzed. The functions realized by the PLAs are in sum-of products form, where the sum is ordinary addition truncated to the highest logic value and the product represents the MIN operation of functions of the input variables that are the interval literal operations. Three heuristics, proposed by G. Pomper and J.A. Armstrong (1981), P.W. Besslich (1986), and G.W. Dueck and D.M. Miller (1987), are compared over sets of random and random-symmetric functions. An exact minimization method that is a tree search using backtracking is described. A reduction in the search space is achieved by considering constrained implicant sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. The case involving only prime implicants is considered, and it is shown that such implicants have marginal value compared to constrained implicant sets. The basis of comparison is the average number of product terms View full abstract»

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  • Setup algorithms for cube-connected parallel computers using recursive Karnaugh maps

    Publication Year: 1991 , Page(s): 217 - 221
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    Optimal setup procedures for cube-connected networks are described. The setup patterns include paths, transpositions, cycles, and one-pass permutations. It is shown that for an N-input cube-connected network, the procedure for paths requires O(log 2 N) steps and O(N) space, the procedure for transportations and cycles requires O(N) steps and O(N) space, and the procedure for permutations takes O(N log2 N) steps and O(N) space. It is also shown that the time complexities of the setup procedures for transpositions, cycles, and permutations can be improved as O(log2 N) by using O(N) processors View full abstract»

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  • A hardware-oriented algorithm for floating-point function generation

    Publication Year: 1991 , Page(s): 237 - 241
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    An algorithm is presented for performing accurate, high-speed, floating-point function generation for univariate functions defined at arbitrary breakpoints. Rapid identification of the breakdown interval, which includes the input argument, is shown to be the key operation in the algorithm. A hardware implementation which makes extensive use of read/write memories is used to illustrate the algorithm View full abstract»

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  • Diagnosabilities of hypercubes under the pessimistic one-step diagnosis strategy

    Publication Year: 1991 , Page(s): 232 - 237
    Cited by:  Papers (37)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    The capabilities of a system-diagnosis technique based on mutual testing are discussed. The technique is applied to hypercube computer systems. A one-step diagnosis of hypercubes that involves only one testing phase, in which processors test each other, is described. Two kinds of one-step diagnosis are presented: the precise one-step diagnosis and the pessimistic one-step diagnosis. Results indicate that the degree of diagnosability of the n-dimensional hypercube (for short, n-cube), where n⩾4, increases from n to 2n-2 as the diagnosis strategy changes from the precise one-step strategy to the pessimistic one-step diagnosis strategy. If the fault bound, the upper bound on the possible number of faulty processors, is kept to the same number n in both cases of diagnosis, then the pessimistic strategy requires fewer testing links per processor than the precise strategy. An algorithm for selecting the bidirectional links in an n-cube for use as testing links is also presented View full abstract»

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  • Theory and design of t-error correcting/d-error detecting (d>t) and all unidirectional error detecting codes

    Publication Year: 1991 , Page(s): 132 - 142
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    The fundamental theory of t-error correcting/d-error-detecting (d>t) and all-unidirectional-error-detecting (t-EC/d-ED/AUED) codes is given. A method for the construction of systematic t-EC/d-ED/AUED codes is presented. The encoding/decoding algorithms for these codes and their implementation are described View full abstract»

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  • On unordered codes

    Publication Year: 1991 , Page(s): 125 - 131
    Cited by:  Papers (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    By extending the results obtained by D. E. Knuth (1986), a parallel unordered coding scheme with 2r information bits is described. Balanced codes in which each codeword contains equal amounts of zeros and ones, with r check bits and up to 2r+1-(r+2) information bits, are constructed. Unordered codes with r check bits and up to 2r+2r-1-1 information bits are designed. Codes capable of detecting 2r-1+[2r/2]-1 unidirectional errors using r check bits are also described. A review of previous work is presented View full abstract»

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  • On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication

    Publication Year: 1991 , Page(s): 205 - 213
    Cited by:  Papers (98)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    Lower-bound results on Boolean-function complexity under two different models are discussed. The first is an abstraction of tradeoffs between chip area and speed in very-large-scale-integrated (VLSI) circuits. The second is the ordered binary decision diagram (OBDD) representation used as a data structure for symbolically representing and manipulating Boolean functions. The lower bounds demonstrate the fundamental limitations of VLSI as an implementation medium, and that of the OBDD as a data structure. It is shown that the same technique used to prove that any VLSI implementation of a single output Boolean function has area-time complexity AT2=Ω(n 2) also proves that any OBDD representation of the function has Ω(cn) vertices for some c>1 but that the converse is not true. An integer multiplier for word size n with outputs numbered 0 (least significant) through 2n-1 (most significant) is described. For the Boolean function representing either output i-1 or output 2n-i-1, where 1⩽in, the following lower bounds are proved: any VLSI implementation must have AT 2=Ω(i2) and any OBDD representation must have Ω(1.09i) vertices View full abstract»

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  • An improved vector-reduction method

    Publication Year: 1991 , Page(s): 214 - 217
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A pipelined vector-reduction method that is based on L.M. Ni and K. Hwang's (1985) symmetric and asymmetric reduction methods is discussed. It is shown that the proposed method is the fastest among known pipelined vector-reduction methods View full abstract»

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Politecnico di Torino
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e-mail: pmo@computer.org