IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 2 • Feb 1991

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Displaying Results 1 - 16 of 16
  • A parasitics extraction and network reduction algorithm for analog VLSI

    Publication Year: 1991, Page(s):145 - 149
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    A transmission line model for the extraction of circuit parasitics in integrated circuits is presented. This model is shown to give a better account of the DC and aC characteristics of interconnects than models incorporating exclusively the R or C components. A network-reduction technique that is used to simplify the extracted RC network at user-specified accuracies to m... View full abstract»

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  • A robust channel router

    Publication Year: 1991, Page(s):212 - 219
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (764 KB)

    A robust channel router with simple heuristics is discussed. This router is able to handle two-layer channels, three-layer channels with two horizontal layers and one vertical layer (HVH), and three-layer channels with two vertical layers and one horizontal layer (VHV). This router uses horizontal layers only for horizontal wires and the vertical layer only for vertical wires. It is robust in the ... View full abstract»

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  • Symbolic generation of constrained random logic cells

    Publication Year: 1991, Page(s):220 - 231
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1148 KB)

    A symbolic cell generator (SYC) that can generate the symbolic layout of a generic CMOS logic cell is presented. It accepts as input a SPICE-like netlist describing circuit components, connectivity, and the list of the I/O pins. Using this generator, the user can specify topological constraints on pin and transistor positions, the maximum lengths of polysilicon and diffusion wires, and a preferred... View full abstract»

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  • Scheduling blocks of hierarchical compiled simulation of combinational circuits

    Publication Year: 1991, Page(s):184 - 192
    Cited by:  Papers (1)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (860 KB)

    Several algorithms for scheduling high-level functional blocks that assume the blocks may not be physically divided and that pseudocycles may be present due to the grouping of elements within blocks are presented. These algorithms rely on dependency information derived from the block-definitions to create a logical (rather than physical) partitioning of the circuit. The partitioned network is sche... View full abstract»

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  • A general greedy channel routing algorithm

    Publication Year: 1991, Page(s):204 - 211
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (852 KB)

    A general approach for the channel routing problem is presented as a framework for a class of heuristic routing algorithms. The algorithm is shown to possess a backtracking capability that increases the chance of completing the routing with a minimum number of tracks. Since the concepts described are general, they can be applied to other channel problems, such as switchbox routing, three-layer rou... View full abstract»

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  • Sensitivity computation in piecewise approximate circuit simulation

    Publication Year: 1991, Page(s):171 - 183
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1104 KB)

    Both direct and adjoint methods are applied to the computation of time-domain transient sensitivities in the already efficient SPECS piecewise approximate circuit simulation environment. By exploiting the event-driven nature of SPECS, the computation, storage, and interpolation of the Jacobians that specify the appropriate linearized circuit during the forward simulation is not required to obtain ... View full abstract»

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  • Estimating the minimum of partitioning and floorplanning problems

    Publication Year: 1991, Page(s):273 - 282
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (616 KB)

    The statistical properties of two combinatorial optimization problems that arise in the physical design of circuits, circuit partitioning, and floorplanning, are discussed. For the partitioning problem, the solutions generated by the Kernighan-Lin (1970) procedure and those generated by a random search are examined. It is shown that in both cases, the Type 3 (Weibull) extreme value distribution pr... View full abstract»

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  • Iterative algorithms for computing aliasing probabilities

    Publication Year: 1991, Page(s):260 - 265
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (540 KB)

    An algorithm, ALG-MK, for computing exact aliasing probabilities in signature analysis is derived from a Markov process model of signature analysis. A previous algorithm, ALG-BL, which was derived from a Boolean expressions formulation of the problem, is reformulated so that it can also be reviewed as being based on a Markov process. Both algorithms compute exact aliasing probabilities in signatur... View full abstract»

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  • A macromodeling algorithm for analog circuits

    Publication Year: 1991, Page(s):150 - 160
    Cited by:  Papers (22)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (864 KB)

    A macromodel is an electrical network containing fewer devices and/or fewer nodes than the circuit it represents. A general-purpose algorithm for the generation of macromodels suitable for circuit simulation is presented. The algorithm is based exclusively on a comparison of the input-output behavior of the macromodel with that to the circuit to be modeled. Because no reliance on any particular pr... View full abstract»

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  • Solution of the hydrodynamic device model using high-order nonoscillatory shock capturing algorithms

    Publication Year: 1991, Page(s):232 - 244
    Cited by:  Papers (65)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (908 KB)

    Simulation results for the hydrodynamic model are presented for an n+-n-n+ diode by use of shock-capturing numerical algorithms applied to the transient model with subsequent passage to the steady state. The numerical method is first order in time, but of high spatial order in regions of smoothness. Implementation typically requires a few thousand time steps. These algorithms... View full abstract»

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  • An adaptation of the interior point method for solving the global routing problem

    Publication Year: 1991, Page(s):193 - 203
    Cited by:  Papers (23)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (812 KB)

    A linear-programming (LP) solution technique is applied to solve the global routing problem. Minimal spanning trees that were found in the subgrid by generating vertical and horizontal lines about the points of a given net and a modified interior point approach that reduces the number of arc constraints which were considered in the routing problem were used to reduce the problem site. An interior ... View full abstract»

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  • A fault model for PLAs

    Publication Year: 1991, Page(s):265 - 270
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    A fault model for programmable logic arrays (PLAs) is discussed. This model maps realistic failures on four classes of faults: multiple stuck-at faults, multiple bridging faults, multiple crosspoint faults, and faults due to breaks in lines. It is shown that multiple stuck-at faults are equivalent to multiple crosspoint faults, multiple bridging faults are sub-equivalent to multiple crosspoint fau... View full abstract»

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  • A submicrometer MOS transistor I-V model for circuit simulation

    Publication Year: 1991, Page(s):161 - 170
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (816 KB)

    A MOSFET I-V model (MOSTSM) that is composed of simple analytical equations applicable down to a 0.5-μm MOSFET operation is proposed. This model provides enhanced performance with respect to gate electric field effects on channel conductance and channel-length modulation in saturation operation. Subthreshold conduction is modeled, and simple and accurate geometrical effect (ch... View full abstract»

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  • Numerical simulator for superconducting integrated circuits

    Publication Year: 1991, Page(s):245 - 251
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (468 KB)

    A numerical simulator for the analysis of Josephson logic circuits that uses numerical methods and dynamic memory allocation, and is capable of simulating a wide variety of superconducting and conventional circuits, is described. The program uses SPICE-like input syntax and is capable of both static and dynamic analysis. The basic operation of Josephson logic is explained and an example simulation... View full abstract»

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  • On river routing with minimum number of jogs

    Publication Year: 1991, Page(s):271 - 273
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (292 KB)

    The one-layer wiring problem of providing a one-to-one connection between two sets of terminals that lie on two horizontal lines by means of wires, which are in the forms of disjoint rectilinear curves on a unit-grid (where one unit is the minimum spacing between two wires), is called the river routing problem. The minimization of horizontal wire segments for a one-layer rectilinear river routing ... View full abstract»

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  • A Markov chain-based yield formula for VLSI fault-tolerant chips

    Publication Year: 1991, Page(s):252 - 259
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (712 KB)

    A yield calculation method for the yield formula of fault-tolerant VLSI chips that improves existing methods and combines generalities, ease of computation, and predictability in approximation levels is presented. The method is concerned with the evaluation of the probability that a chip is acceptable given n defects. This is accomplished by introducing a Markov chain model in which each ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu