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Computers and Digital Techniques, IEE Proceedings E

Issue 1 • Date Jan 1991

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Displaying Results 1 - 8 of 8
  • Novel cell architecture for bit level systolic arrays multiplication

    Page(s): 21 - 26
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    A novel cell architecture for bit level systolic array multiplication is presented. It is used for the design of a serial-parallel and an iterative pipelined multiplier. The new architecture is a result of combining, in a novel way, the operation of a two gated full-adder cell used in conventional multipliers. The new cell circumvents the insertion of zeros in structures with contraflow data streams. As a result, the array is used with 100% efficiency, and the throughput rate is doubled in comparison to most systolic arrays using the contraflowing approach. This is achieved without any increase in hardware, nor the use of a special clock circuitry. Performance analysis of the new multipliers and existing ones has shown the superiority of the new architecture. View full abstract»

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  • Disjoint decomposition of Boolean functions

    Page(s): 48 - 56
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    The minimisation of Boolean functions is a classical problem. The paper deals with the set of functions which satisfy the equation f(X)=h(g(X1),X2) where the variable set X is given by the disjoint union of any sets X1 and X2. The author presents an efficient method in the Boolean domain which is based on the theory of Boolean differential calculus and the spectral development using the Walsh transform. View full abstract»

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  • Development of a blackboard shell with context blackboard-based controlloop

    Page(s): 1 - 12
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1284 KB)  

    Best-match-pair is proposed as a new strategy for the control mechanism of blackboard systems. A generalised blackboard shell with the strategy as the control loop is proposed, which evaluates both solution areas and knowledge sources explicitly. This approach improves the system performance by providing a balanced status feedback between potential knowledge sources and promising solution areas for system control and replanning. It also enhances the system performance by supporting viewpoint reasoning, shadow reasoning, and various metalevel applications, e.g., viewpoint explanation, knowledge acquisition, etc. View full abstract»

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  • New iterative construction approach to routing with compacted area

    Page(s): 57 - 71
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1036 KB)  

    The new iterative construction approach presented consists of three algorithms, namely, channel expansion routing, track assignment, and module location refinement. These algorithms, contrary to the conventional methods implemented with a sequence of tools separately, are linked with a common data structure which guarantees a maximal compatibility. With an initial nonoverlapping placement as input, the iterative construction approach generates a final layout with a more compacted area than the layout result from the one-dimensional compactor or some of two-dimensional compactors. Several layout examples in the literature are tested to show the effectiveness of the approach. View full abstract»

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  • Tristage Hough transform for multiple ellipse extraction

    Page(s): 27 - 35
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (988 KB)  

    Presents a novel tristage technique for ellipse extraction based on decomposing the problem into sequentially executed stages. Candidate ellipse centres are determined using an improved centre-finding procedure and novel Hough-based procedures extract the remaining parameters in two further stages. Although multistage parameter extraction is not new, many of the problems that exist in previous schemes are resolved. In the new technique, the dimensionality of the accumulator arrays used does not exceed two, while their ranges are predefined. Memory savings are therefore significant. Concentric ellipses of the same orientation are shown to be extracted with little extra computational demand. Two extensions of the tristage technique to multiple ellipse extraction are presented and compared. View full abstract»

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  • Test generation within an expert system environment

    Page(s): 36 - 40
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    Gate-level test pattern generation (TPG) techniques are inadequate when considering the complexity and variety of today's circuits. Hence, more abstract approaches must be developed so that TPG efficiency can be increased and the inherent bottleneck between test planning and TPG reduced. As an expert system attempts to model human reasoning, functional TPG approaches must be used within such an environment as opposed to algorithmic gate-level methods which are beyond the capability of human understanding, memory and reasoning, whereas functional approaches map directly to the human thought process. The paper discusses how such a test generation approach can be used within an expert system, furthermore a number of heuristics are described to show how TPG can be simplified within such an environment. View full abstract»

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  • Analytic models for performance evaluation of single-buffered banyan networks under nonuniform traffic

    Page(s): 41 - 47
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    The performance of single-buffered banyan networks under certain nonuniform traffic patterns had been studied by Garg and Huang (1988). However, the models used are over simplified and the results obtained may deviate from exact values significantly. Alternative models to achieve more accurate performance estimates are presented. In these models, the destinations of blocked packets residing in the buffers of nodes at stage 1 (and perhaps stage 2, depending on the traffic matrix) are memorised. Compared with those adopted by Garg and Huang, the models are only slightly more complicated. By viewing banyan networks as queueing systems, the article applies the Little formula to compute the average packet delays. View full abstract»

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  • Expert compactor: a knowledge-based application in VLSI layout compaction

    Page(s): 13 - 26
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    A new application of artificial intelligence techniques in automatic compaction design for a VLSI mask layout is presented. To overcome the shortcomings of iterative search through a large problem space within a working memory, and therefore, to speed up the runtime of compaction, a set of rule-based region query operations and knowledge-based techniques for the plane sweep method are presented in this system. Experimental results have explored the possibility of using expert system technology to automate the compaction process by reasoning about the layout design, applying the sophisticated expert rules to its knowledge base. View full abstract»

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