Issue 3 • Date Aug 1988
The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer fabrication. Certain of these scheduling rules are derived by restricting attention to the sub-set of stations that are heavily utilized, and by using a Brownian network model, which approximates a multi-class queuing network model with dynamic control capability. Three versions of the wafer fabrication model, which differ only by the number of servers present at particular stations, are studied. The three versions have one, two, and four stations, respectively, that are heavily utilized (near 90% utilization). The simulation results indicate that scheduling has a significant impact on average throughput time, with larger improvements coming from discretionary imput control than from lot sequencing. The effects that specific sequencing rules have are highly dependent on both the type of input control used and the number of bottleneck stations in the fabrication. View full abstract»
Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed View full abstract»
A simple physical model is proposed for bulk imaging effects during latent image formation in a resist layer. The model considers refraction at the air-resist interface, as well as depthwise defocus of the lateral intensity distribution within the resist layer. The approach represents a first-order correction to the vertical propagation model used in conventional photolithography simulation, yet preserves the data structures of simulators such as SAMPLE and SPESA, and requires only a modest increase in computational effort. Comparison of simulated resist profiles with published experimental data shows that this model qualitatively explains the asymmetries in photolithographic response observed as a function of focus offset position in a single layer resist process. The question of the optimum focal position within the resist layer is discussed using simulated focus-exposure diagrams and the concept of effective defocus View full abstract»
An experiment was conducted to determine if contrast tuning could be performed on an automated track developer using a standard spray versus an ultrasonic nozzle. GaAs wafers were patterned with a linear variable neutral density filter (LVNDF) and developed by spray and an ultrasonic nozzle. The ultrasonic nozzle produced a lower chemical contrast than the standard spray development. This lower chemical contrast used in conjunction with image reversal makes photoresist sidewalls more retrograde, which is advantageous in GaAs processing for metal liftoff. In addition to contrast tuning, the LVNDF technique is described that was used to quickly and easily compare the contrasts of the two development systems. With the LVNDF mask, chemical contrast as well as process uniformity could be quickly measured View full abstract»
Aims & Scope
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.