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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • Date Mar 1991

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Displaying Results 1 - 12 of 12
  • A new transition count method for testing of logic circuits

    Publication Year: 1991, Page(s):407 - 410
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The authors propose a transition count method for detecting faults in single- and multiple-output logic circuits. It can be extended to sequential circuits in which scan design is incorporated. This method is called double transition count (DTC) testing for single-output circuits and multiple transition count (MTC) testing for multiple-output circuits. It is shown that the detectability of faults ... View full abstract»

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  • Design representation in Movie

    Publication Year: 1991, Page(s):335 - 345
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    An environment for silicon compilation tools in which module generators can be created, maintained, and operated on is defined. A module is defined by its specification, which can be hierarchically parameterized. Instantiation is based on a set of built-in rules including geometrical design rules and composition rules for modules. An abstraction of the functionality is created by defining a formal... View full abstract»

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  • Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement

    Publication Year: 1991, Page(s):399 - 406
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    Clustered faults that affect the manufacture of integrated circuits are modeled by a simulation approach in which the fault formation is a function of time. In one such approach, the probability of generating a fault in a given subarea of an integrated circuit at any given time is assumed to depend on the number of faults already in that area and on the number of faults in the nearest-neighbor adj... View full abstract»

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  • Optimum and heuristic algorithms for an approach to finite state machine decomposition

    Publication Year: 1991, Page(s):296 - 310
    Cited by:  Papers (30)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1468 KB)

    Optimum and heuristic algorithms for the general decomposition of finite state machines (FSMs) such that the sum total of the number of product terms in the one-hot-coded and logic-minimized submachines is minimum or minimal are presented. This cost function is much more reflective of the area of an optimally state-assigned and minimized submachine than the number of states/edges in the submachine... View full abstract»

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  • An efficient verifier for finite state machines

    Publication Year: 1991, Page(s):326 - 334
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    The correctness-checking problem of a finite-state machine is considered. The concept of machine cover is revived and used as the basis of the formulation of the verification problem of the design correctness of finite-state machines. The concept of machine cover enables the verifier to efficiently check the sufficiency. The verifier checks to see if the implementation is correct with respect to i... View full abstract»

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  • Test efficiency analysis of random self-test of sequential circuits

    Publication Year: 1991, Page(s):390 - 398
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    Motivated by the work of K. Kim et al. (1988) and A. Krasniewski and S. Pilarski (1989), the problem of test efficiency in random testing of sequential circuits using built-in self-test (BIST) techniques is addressed. It is shown that, given a circuit with n primary inputs and the goal of maximizing expected pattern coverage, different pattern-sampling distributions for its 2n ... View full abstract»

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  • Numerical device modeling for electronic circuit simulation

    Publication Year: 1991, Page(s):366 - 375
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    Numerical MOSFET modeling based on multidimensional Bernstein interpolation is presented as a means to improve simulation efficiency. Device operating-point information is extracted from prestored table values using functional reconstruction during transient simulation. The formulation of the numerical model conforms to the requirements of electronic circuit simulators which use the Newtonian-Raph... View full abstract»

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  • A transformational approach to synthesizing combinational circuits

    Publication Year: 1991, Page(s):286 - 295
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    VAR, a transformational approach for obtaining multilevel logic synthesis results, is described. Suppressed variable permutation and complementation (SVPC) transformations which are powerful and can be economically realized are introduced. Each SVPC transformation can be viewed as an identity mapping on the n-cube, except on an (n-r)-subcube (defined by r fixed ... View full abstract»

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  • Switch-level simulation using dynamic graph algorithms

    Publication Year: 1991, Page(s):346 - 355
    Cited by:  Papers (7)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (908 KB)

    A model for MOS transistors that is suitable for logic simulation of VLSI circuits is presented. It is based on the concept of a dynamically directed switch (DDS). As in other switch-level models, the circuit is viewed as a graph whereon transistors are represented by directed edges and circuit nodes are represented by vertices. The problem of finding the steady-state response of the circuit is sh... View full abstract»

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  • Irredundant interacting sequential machines via optimal logic synthesis

    Publication Year: 1991, Page(s):311 - 325
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1452 KB)

    The authors develop optimal synthesis procedures for interacting nonscan sequential circuits composed of interacting finite state machines. For each of the different classes of redundancies, the authors define don't care sets, which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. It is shown that notions of sequential don't cares and cond... View full abstract»

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  • A charge sheet capacitance model of short channel MOSFETs for SPICE

    Publication Year: 1991, Page(s):376 - 389
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    An analytic charge sheet capacitance model for short-channel MOSFETs is derived and implemented in SPICE. It is based on a surface potential formulation which computes the approximate surface potential without iterations. The DC current, charges, and their first and second derivatives are continuous under all operating regions. Equations for node charges are derived to guarantee charge conservatio... View full abstract»

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  • GORDIAN: VLSI placement by quadratic programming and slicing optimization

    Publication Year: 1991, Page(s):356 - 365
    Cited by:  Papers (236)  |  Patents (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1004 KB)

    The authors present a placement method for cell-based layout styles. It is composed of alternating and interacting global optimization and partitioning steps that are followed by an optimization of the area utilization. Methods using the divide-and-conquer paradigm usually lose the global view by generating smaller and smaller subproblems. In contrast, GORDIAN maintains the simultaneous treatment ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu