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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1991

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Displaying Results 1 - 17 of 17
  • Correction to 'The De Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI'

    Publication Year: 1991
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (89 KB)  

    Corrections to the galley proof of the above-titled paper by the authors (see ibid., vol.38, no.4, p.567-81 (1989)) that were inadvertently omitted from the published paper are given.<> View full abstract»

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  • Correction to 'Parallel algorithm for Delaunay triangulation on orthogonal tree network in two and three dimensions

    Publication Year: 1991
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB)  

    Some material is added to theorem 4 of the above-titled paper by the authors (see ibid., vol.39, no.3, p.400-4 (1990)).<> View full abstract»

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  • A synthesis approach to design optimally fault tolerant network architecture

    Publication Year: 1991 , Page(s): 94 - 100
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    A synthesis approach to the design of a class of regular networks which provide optimal fault tolerance and are of small diameter is presented. The approach makes it possible to design a regular network in the form of a directed graph when the number of nodes n and the number of connections per node d are given, for any n and d. The designed graph will have node connectivity d and a diameter proportional to [ogd n] View full abstract»

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  • An optimal systolic array for the algebraic path problem

    Publication Year: 1991 , Page(s): 100 - 105
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    A systolic array design for the algebraic path problem (APP) is presented that is both simpler and more efficient than previously proposed configurations. This array uses N2 orthogonally connected processing elements and requires 2N I/O connections. Total computation time is 5N-2, which is the minimum time possible in a systolic implementation. The data pipelining rate is one, so no pipeline interleave is required. For multiple problem instances a block pipeline rate of N can be achieved, which is optimal for an array of N2 processing elements View full abstract»

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  • Embedding rectangular grids into square grids

    Publication Year: 1991 , Page(s): 46 - 52
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    It is shown that two-dimensional rectangular grids of large aspect ratio can be embedded into rectangular grids of smaller aspect ratios with small expansion and dilation. In particular, width can be reduced by a factor of up to two with optimal expansion, i.e. when the host rectangle is the smallest sufficient to contain the guest, and optimal dilation, i.e., two. A width reduction factor of three can be obtained with optimal expansion and dilation three. In general, any rectangular grid can be embedded into a square grid that is no more than unity larger on the side than the minimum possible, with dilation no more than three. These results improve on those previously obtained, in which dilation of better than 18 could not be guaranteed. They might be applicable to more complex grid embedding problems, such as embedding multidimensional grids into hypercubes View full abstract»

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  • Optimal VLSI sorting with reduced number of processors

    Publication Year: 1991 , Page(s): 105 - 110
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    A new parallel architecture is presented which has p processors and N=n2 memory locations, each consisting of 2s bits. The proposed organization can sort N s-bit numbers, where s=O((1+ε) log N), ε>0, in time t=O(N log N÷p), for p in the range 1 to √N log √N. This result is optimal in the sense that the product of the number of processors and the parallel sorting time is equal to the sequential complexity of sorting. Also, the constant factors involved in the algorithm complexity are relatively small. When p=√N log √N, the time required for sorting N numbers on the proposed organization is O(√N), which is the same time required by a two-dimensional mesh array, a mesh of trees organization, or a pyramid computer, all with O(N) processors, to sort N numbers View full abstract»

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  • The twisted N-cube with application to multiprocessing

    Publication Year: 1991 , Page(s): 88 - 93
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    It is shown that by exchanging any two independent edges in any shortest cycle of the n-cube (n⩾3), its diameter decreases by one unit. This leads to the definition of a new class of n-regular graphs, denoted TQn, with 2n vertices and diameter n-1, which has the (n-1)-cube as subgraph. Other properties of TQn such as connectivity and the lengths of the disjoints paths are also investigated. Moreover, it is shown that the complete binary tree on 2n-1 vertices, which is not a subgraph of the n-cube, is a subgraph of TQn. How these results can be used to enhance hypercube multiprocessors is discussed View full abstract»

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  • Absolute minimization of completely specified switching functions

    Publication Year: 1991 , Page(s): 53 - 65
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1200 KB)  

    For the automated design of PLAs (programmable logic arrays) with a minimum size, computationally efficient procedures are needed that can minimize functions of a large number of variables. For such minimization procedures, excessively long processing time and an excessively large memory requirement are major problems to overcome. An absolute minimization procedure is presented for standard PLAs with reduced computation time and memory space. The improvement achieved by this procedure, which is based on the decomposition of ratio sets, is mainly due to the detection of all essential prime implicants during the derivation of inclusion functions and to the merger of two procedures previously published by R.B. Cutler and S. Muroga (1987) into one efficient procedure View full abstract»

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  • Approximation and intractability results for the maximum cut problem and its variants

    Publication Year: 1991 , Page(s): 110 - 113
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    The maximum cut problem is known to be an important NP-complete problem with many applications. The authors investigate this problem (which they call the normal maximum cut problem) and a variant of it (which is referred to as the connected maximum cut problem). They show that any n-vertex e-edge graph admits a cut with at least the fraction 1/2+1/2n of its edges, thus improving the ratio 1/2+2/e known before. It is shown that it is NP-complete to decide if a given graph has a normal maximum cut with at least a fraction (1/2+ε) of its edges, where the positive constant ε can be taken smaller than any value chosen. The authors present an approximation algorithm for the normal maximum cut problem on any graph that runs in O((e log e+n log n )/p+log p×log n) parallel time using p(1⩽pe+n) processors that guarantees a ratio of at least [1/2+1/2n], given a matching of size e/n in G. The authors take up the connected maximum cut problem and show that, unlike the normal maximum cut problem, this problem admits an infinity of instances where the fraction of the edges in the connected maximum cut is arbitrarily close to zero. They then show that the connected maximum cut problem is NP-complete even for planar graphs, in clear contrast to the normal maximum cut problem, which is solvable in polynomial time on planar graphs View full abstract»

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  • Expanding the range of convergence of the CORDIC algorithm

    Publication Year: 1991 , Page(s): 13 - 21
    Cited by:  Papers (37)  |  Patents (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    The limitations on the numerical values of the functional arguments that are passed to the CORDIC computational units are discussed, with a special emphasis on the binary, fixed-point hardware implementation. Research in the area of expanding the allowed ranges of the input variables for which accurate output values can be obtained is presented. The methods proposed to expand the range of convergence for the CORDIC algorithm do not necessitate any unwidely overhead calculation, thus making this work amenable to a hardware implementation. The number of extra iterations introduced in the modified CORDIC algorithms is significantly less than the number of extra iterations discussed elsewhere. This reduction in the number of extra iterations will lead to a faster hardware implementation. Examples demonstrate the usefulness of the methods in realistic situations View full abstract»

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  • Functional fault simulation as a guide for biased-random test pattern generation

    Publication Year: 1991 , Page(s): 66 - 79
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1276 KB)  

    An approach to the generation of test patterns for implementation-level faults is presented. The approach involves fault simulation on a functional-level description of a combinational VLSI design, together with an appropriate functional fault model. The methodology uses the difference fault model (DFM), a formal abstraction of the faults at the implementation level, as the basis for fault simulation at the functional level. Incremental information from fault simulation results provides guidance for the generation of nonuniformly random test patterns using a backtracing process. The quality of the generated patterns is measured in terms of their coverage of implementation faults View full abstract»

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  • Stochastic modeling and analysis of propagation delays in GaAs adders

    Publication Year: 1991 , Page(s): 31 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    The problem of how to assess the probability distribution function (PDF) of the propagation delay for different adder types in order to compare their sensitivities to stochastic changes of gate delays is addressed. An original methodology that solves the problem for combinational circuits of arbitrary topology (without loops) is introduced. Its capabilities are demonstrated through the modeling and analysis of propagation delays in GaAs adders. This methodology is directly applicable to a number of analogous problems in other fields View full abstract»

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  • Improving disk performance via latency reduction

    Publication Year: 1991 , Page(s): 22 - 30
    Cited by:  Papers (17)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    It is shown that in many environments the rotational latency and the rotational position sensing (RPS) miss delay are the major contributors to a disk's basic service time. A sensitivity study using a simple analytical queueing model shows that a reduction in these two components (both of which are related to the rotation of disk drives) has the greatest impact in reducing the disk's basic service time and in turn produces the greatest improvement in overall subsystem performance. While the most straightforward way to reduce latency and RPS miss penalty would be to increase the disk's rotation speed, there are some limitations to such an approach. Several alternatives to reducing latency and RPS miss penalty are proposed and explored, and their performance is analyzed using analytical queuing models View full abstract»

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  • A network flow approach to the reconfiguration of VLSI arrays

    Publication Year: 1991 , Page(s): 118 - 121
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A technique for reconfiguring a two-dimensional VLSI array with faulty cells is presented. A network flow model of the problem is used to provide an algorithm for connecting the functional cells of the array so that they simulate a fault-free array of smaller size. The interconnection wires are routed inside horizontal and vertical channels according to the Manhattan model. Experimental results indicate that the algorithm has good performance in practice View full abstract»

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  • RIDDLE: a foundation for test generation on a high-level design description

    Publication Year: 1991 , Page(s): 80 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    A formal approach to the analysis of a combinational circuit described at the high level is presented. It produces information conducive to the acceleration of test generation algorithms. This analysis yields, as its main product, information which can be used to reduce the amount of effort expended during backtracing, by guiding this process towards decisions (assignments) less likely to cause conflicts and minimizing the amount of work between backtracks. RIDDLE, an algorithm which performs this analysis in time linear in the number of signals, is introduced. Experimental results for the special case of combinational gate-level designs are also given View full abstract»

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  • Minimum spanning trees of moving points in the plane

    Publication Year: 1991 , Page(s): 113 - 118
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    Consideration is given to the following problem. Preprocess n moving points in a plane, such that the Euclidean minimum spanning tree of these points at a given time t can be reported efficiently. In the result, if the moving points are in k-motion, after an O(kn4 log n ) time preprocessing step and using O(m) space to store the preprocessing result, the Euclidean minimum spanning tree at t can be reported in O(n) time, where m denotes the number of changes of the Euclidean minimum spanning tree of these points from time t=0 to time t=∞ View full abstract»

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  • An adaptive and fault tolerant wormhole routing strategy for k -ary n-cubes

    Publication Year: 1991 , Page(s): 2 - 12
    Cited by:  Papers (175)  |  Patents (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    The concept of virtual channels is extended to multiple virtual communication systems that provide adaptability and fault tolerance in addition to being deadlock-free. A channel dependency graph is taken as the definition of what connections are possible, and any routing function must use only those connections defined by it. Virtual interconnection networks allowing adaptive, deadlock-free routing are examined for three k-ary n-cube topologies: unidirectional, torus-connected bidirectional, and mesh-connected bidirectional View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org