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Communications, IEEE Transactions on

Issue 5 • Date May 1978

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Displaying Results 1 - 25 of 38
  • [Front cover and table of contents]

    Page(s): 0
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    Freely Available from IEEE
  • Through the digital processor

    Page(s): 489 - 492
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  • Introduction to Papers on TDM/FDM Transmultiplexers

    Page(s): 697 - 698
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  • [Back cover]

    Page(s): 0
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  • A 4800 Bit/s Microprocessor Data Modem

    Page(s): 493 - 498
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    The development of a new 4800 bit/s data modem, based on real-time digital signal processing by program controlled microprocessors, is described. The modem is fully compatible with the CCITT Recommendations V.27 bis and V.27 ter. In the microprocessor modem, all the digital signals are processed by one general purpose microprocessor unit only and no hardware multiplier is employed. A series of processing cycle reduction tactics have allowed an off-the-shelf microprocessor to handle all the modem functions in a real-time environment. Particularly noteworthy, among these tactics, is the use of a decision feedback equalization algorithm. Numbers of multiplications, which are required for a conventional linear equalization, are shown to be obviated with the DFE algorithm. It is also shown that the DFE facilitates a certain timing phase control method. The microprocessor modem is extremely flexible because of its software controlled nature, and through programming it will provide a variety of additional functions. View full abstract»

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  • LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem

    Page(s): 499 - 506
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    This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the type A \times B + C \rightarrow D and the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10-5at S/N = 17.6 dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described. View full abstract»

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  • Digital Signal Processing with Program Synchronization Between Two Microprocessors

    Page(s): 513 - 517
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    This paper addresses the synchronization problems which arise when real-time signal processing is performed in a multimicroprocessor machine. An experimental machine composed of two specialized microprocessors has been assembled: one to compute correlation and convolution products with a high thruput; the second one is a general purpose microprocessor which efficiently handles independent tasks on its various interrupt levels. The signal processing was decomposed into a sequence of elementary time dependent tasks executed in an appropriate order. Due to microprocessor specialization, the microprocessors had to give assistance to each other, and a tight synchronization between the programs run by each of these was necessary. This machine has been used successfully in data communication applications. View full abstract»

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  • Tamed Frequency Modulation, A Novel Method to Achieve Spectrum Economy in Digital Transmission

    Page(s): 534 - 542
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    This paper describes a new type of frequency modulation, called Tamed Frequency Modulation (TFM), for digital transmission. The desired constraint of a constant envelope signal is combined with a maximum of spectrum economy which is of great importance, particularly in radio channels. The out-of-band radiation is substantially less as compared with other known constant envelope modulation techniques. With synchronous detection, a penalty of only 1 dB in error performance is encountered as compared with four-phase modulation. The idea behind TFM is the proper control of the frequency of the transmitter oscillator, such that the phase of the modulated signal becomes a smooth function of time with correlative properties. Simple and flexible implementation schemes are described. View full abstract»

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  • An Improved Method for Digital SSB-FDM Modulation and Demodulation

    Page(s): 720 - 725
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    A new method for digital implementation of SSB-FDM modulation and demodulation is presented, which utilizes the FFT algorithm to reduce the multiplication rate. The hardware realization of the presented method is shown to be the simplest; it consists of only an FFT processor and a set of complex bandpass filters which operate at the same rate as the input baseband sequences; no signal conversions are required prior to FFT processing. Simple and practical approaches are presented for design and implementation of the EFT processor and the set of complex bandpass filters. Design examples, which are made for implementation of a TDM-FDM translator at the supergroup level, show that the proposed method can attain the minimum multiplication rate among methods previously reported. View full abstract»

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  • Carrier and Clock Recovery for 8 PSK Synchronous Demodulation

    Page(s): 528 - 533
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    Synchronous demodulation of Phase-shift-keyed transmissions requires the recovery of carrier and clock timing signals. Envelope detection of the 70 MHz IF signal is used to recover clock, and baseband processing is used to recover carrier for an 8 PSK digital radio with a data rate of 90 Mbits/s in the 11 GHz band. A sequential phase detector is used in a high noise application. Two versions of the carrier recovery circuit are presented. The first one employs hot carrier diode quads to form a compound Costas loop. The second one employs ECL exclusive-OR gates. Emphasis is placed on providing high performance while conserving energy, space, and manufacturing cost. View full abstract»

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  • A Bandwidth Compressive Modulation System Using Multi-Amplitude Minimum Shift Keying (MAMSK)

    Page(s): 543 - 551
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    A bandwidth compressive modem making use of multiamplitude minimum shift keying (MAMSK) has been designed and implemented in a laboratory environment at microwave frequencies. This system achieves a substantial bandwidth reduction over binary PSK and operates within 0.5 dB of theoretical performance. A number of easily implemented microwave transmitters have been designed to generate the required set of 16 signals. The receiver has been designed to work at 1 Mbit/s and contains the necessary phase tracking, AGC, and symbol synchronization loops as well as a lock detector, SNR estimator and provisions for differential decoding. This paper describes this entire system and presents the experimental results. View full abstract»

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  • Signal-to-Noise Analysis of a PCM Voice System Based on Analog/Digital Filtering

    Page(s): 653 - 659
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    In the field of communications, an ever-increasing number of system functions is realized in digital form. In this context, the problem of economical analog/digital conversion becomes an important issue. The cost of analog/digital conversion, however, is often dominated by the associated filters required for the prevention of foldover distortion. For this reason, an approach characterized by analog filtering (with relaxed requirements) before A/D conversion, and additional, digital, time-shared filtering after A/D conversion, becomes an attractive solution. In this paper, the signal-to-noise ratio of such a system is analyzed. The analysis includes quantization noise and overload distortion from the analog/digital conversion process, additional noise due to codec imperfections and round-off noise from the digital filters and interpolators. A design example, that was also implemented in hardware, demonstrates that the specifications of the CCITT can be easily met. View full abstract»

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  • Development of a TDM/FDM Transmultiplexer

    Page(s): 726 - 733
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    Recently, digital systems such as digital telephone switching systems and digital transmission paths are being introduced more and more into communications networks in which signals are handled with Time Division Multiplex (TDM). There still exists, on the other hand, a number of analog transmission paths in which signals are multiplexed with Frequency Division Multiplex (FDM). Therefore, it is important to develop a scheme to interconnect efficiently TDM and FDM systems. Transmultiplexer, which is an equipment directly converting PCM.TDM signals and SSB.FDM signals with each other, is expected to provide an efficient interconneetion between TDM and FDM systems. Authors have developed an experimental transmultiplexer which can provide mutual conversion between a 24-channel PCM primary group (1.544 Mbits/s) and two 12-channel FDM basic groups (60-108 kHz). The developed equipment is designed so as to achieve reduction of the computation rate and simplicity of the hardware by the following techniques: (1) The FFT (Fast Fourier Transform) technique is used to optimize the filtering and multiplexing processes. (2) The spectrum reversion of odd-numbered channel signals is achieved by inverting the sign bits of the PCM signals every other frame. (3) The bandpass sampling technique is applied to obtain SSB.FDM signals directly without frequency shifts at analog FDM stages. In order to evaluate the characteristics of the developed transmultiplexer, experiments have been conducted by connecting it with FDM terminal equipments. The experimental results showed that the transmultiplexer can offer better performance than the tandem connection of standard PCM multiplex equipments and standard FDM terminal equipments with reasonable hardware. View full abstract»

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  • A High-Speed FFT Processor

    Page(s): 690 - 696
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    A high-speed, low-power, fast Fourier transform (FFT) processor is described in this paper. The FFT processor is designed around parallel arithmetic functions (16 by 16 multiplier and 16-bit adders) and can operate up to a 17.0-MHz clock rate. It performs a 128-point FFT in 250 μs at 16-MHz clock rate and therefore can be used for applications such as frequency-division multiplexing/timedivision multiplexing (FDM/TDM) transmultiplexer. The processor was designed and tested according to the design specifications. Its standalone feature permits its use in a variety of systems employing spectral analysis. The high-speed requirements are met by a real-time address generation scheme. The design can be used for a higher order FFT by providing extra memory space. View full abstract»

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  • Digital Processing Techniques in the 60 Channel Transmultiplexer

    Page(s): 698 - 706
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    Techniques applied to the digital processing of speech and signaling in a 60 channel FDM to 30 channel PCM converter are presented. Great efficiency is achieved through connecting a particular type of Fourier Transform computer to a polyphase network in which coefficient symmetries are exploited. Digital processing parameter values have been chosen so as to meet specified performance objectives. Realization of a laboratory model is outlined and measured performance is reported. Adequacy of the various options retained for the digital processing is confirmed by the experimental results. View full abstract»

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  • A Microprocessor-Based PSK Modem for Packet Transmission Over Satellite Channels

    Page(s): 552 - 564
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    This paper describes a microprocessor-based modem developed for use in a packet switching network over satellite channels. This digital modem can process both BPSK and QPSK packets with near optimum error rate performance over channels with marginal signal energy-to-noise density ratio. Of principal concern is the development of the discrete time algorithms which form the basis of the microinstruction program. The processing of a packet can be decomposed into two basic stages: (1) the detection of the packet preamble and the rapid estimation of signal parameters (symbol timing and carrier frequency offset) for the specific packet, and (2) the demodulation of the data portion of the packet including the tracking of both symbol timing and carrier offset phase, phase ambiguity resolution and data symbol estimation. The paper concludes with details on the performance of the modem under operational conditions and a brief discussion of implementation of the processor. View full abstract»

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  • On the Design of Quantizers for DPCM Coders: Influence of the Subjective Testing Methodology

    Page(s): 565 - 572
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    In the Candy design procedure for DPCM quantizers, the subject is given a specific task to perform. We test the hypothesis that the form of this task influences the results that are obtained. In one experiment the viewers were permitted unlimited time to evaluate noise visibility; in another test using a different testing procedure viewing time was reduced to one second. Visibility functions were obtained from these tests, and quantizers were designed and then evaluated on the basis of impairment ratings of coded pictures. Our results indicate that the design procedure is indeed sensitive to the viewing conditions. View full abstract»

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  • Separation of NTSC Signals by Minimum Mean Square Error Filters and Adaptive Filters

    Page(s): 583 - 593
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    Two techniques for separating a composite NTSC signal into luminance and chrominance components are developed and compared. In the first technique, fixed filters, which are based upon minimum mean square error estimators, are designed. It is shown that, when samples from successive lines are used, these filters have a comb structure in the region of the frequency spectrum in which the luminance and chrominance signals overlap. In the second technique, the composite signal is filtered by several filters, and the outputs of the filters are selected dependent upon the local characteristics of the picture. Both recursive and nonrecursive filters are considered, the criterion for selecting between filters is investigated and the effect of delayed decisions is determined. The various filters are compared using subjective criterion and a number of quantitative criterion. The relationships between the quantitative and qualitative criterion are stated. View full abstract»

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  • A Three-Dimensional Spatial Non-Linear Predictor for Television

    Page(s): 578 - 583
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    This paper presents a three-dimensional non-linear prediction technique for use in differential pulse code modulation systems used to encode television signals. The prediction is a weighted sum of three estimates called representatives. Each representative is a nonlinear estimate based on previous pels in one of three planes containing the pel to be predicted. The paper contains an explanation of the technique, results of computer simulations of the algorithm and a comparison of the algorithm with other prediction procedures. The predictor is relatively insensitive to image statistics. Errors in the predictor input decay out with time. View full abstract»

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  • A Practical Design Approach to Decision Feedback Receivers with Conventional Filters

    Page(s): 679 - 689
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    A method for designing conventional filters for decision feedback systems is described. Practical considerations, such as error propagation effect, timing inaccuracy and complexity, are incorporated in the design rules. In particular, non-band-limited noisy transmission channels and channels impaired by bandwidth limitation are investigated. In addition, noise and bandwidth limitations are taken into account simultaneously. The design approach is based upon polynomial descriptions which reveal simple relationships between the forward and feedback path, a stability measure which is representative of the error propagation, and an evaluation in terms of Laguerre polynomials. Results of simulations in hardware are given by way of a practical example and a binary regenerative transmission system for coaxial cables is studied. View full abstract»

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  • A Twelve-Channel Digital Echo Canceler

    Page(s): 647 - 653
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    We describe a recently constructed 12-channel digital echo canceler that interfaces directly with the 8-bit μ255 PCM now standard for digital transmission in the telephone plant. The four most interesting features of the canceler are time sharing of circuitry to reduce per channel costs, floating-point multiplication, loop-gain normalization, and the use of a test channel for fault detection. Extensive laboratory and field testing has shown the canceler to be working well. View full abstract»

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  • Modulation Considerations for a 91 Mbit/s Digital Radio

    Page(s): 523 - 528
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    The DRS-8 is a 91 Mbit/s long haul digital radio system designed for use in the Canadian 8 GHz frequency band. This paper discusses the considerations which lead to the choice of Quadrature Partial Response Signaling (QPRS) for this application. A method of implementing QPRS that circumvents power amplification difficulties and permits the use of simple conventional filtering and equalization is presented. The computer analysis program and the design strategy used in the system filter design are described. Details of the signal shaping filters as well as details of carrier and clock synchronization are given. Finally, measured system performance is presented and compared with computed performance. View full abstract»

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  • TDM-FDM Conversion Requiring Reduced Computation Complexity

    Page(s): 707 - 719
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    We present an approach to perform the conversion between two widely used multiplexing techniques in telephony, time division, multiplex (TDM) to frequency division multiplex (FDM), using digital signal processing techniques. By exploiting some results from the theory of computational complexity we reduce considerably the number of computations required. Furthermore the use of only nonrecursive (FIR) filters whose coefficients are expressed in the canonical signed digit code permits a 16 bit implementation requiring no multiplications and only additions with concurrent shifts which further simplifies the required circuitry. View full abstract»

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  • On the Design of Quantizers for DPCM Coders: A Functional Relationship Between Visibility, Probability and Masking

    Page(s): 573 - 578
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    Visibility functions measure the relative visibility of noise added to a picture at those points where some measure of local activity exceeds a given threshold. The functions are obtained from a series of subjective experiments and vary with the content of the picture. Visibility functions have been used to design quantizing characteristics for DPCM coding of monochrome and color signals and for three-dimensional transform coding. We consider an alternative approach to determining the visibility function that obviates the need for repeated picture-dependent subjective tests. The visibility function is assumed to consist of two parts, a picture-dependent component and viewer-dependent component (referred to as the masking function). The visibility function may be approximated by the quotient of a probability density function raised to a power and the masking function. The role of probability is found to be weaker where the viewer has more opportunity to scrutinize the picture. View full abstract»

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  • Digital TDM-FDM Translator with Multistage Structure

    Page(s): 734 - 741
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    In this paper, a new digital signal processing algorithm for the digital TDM-FDM translator is proposed. The digital TDM-FDM translator, which performs a direct translation between two multiplex formats in the telephone network (time-division-multiplexing (TDM) and frequency-division-multiplexing (FDM)) by using digital techniques, has advantages in accuracy and stability of characteristics over equivalent analog equipments. However from the economical point of view, it largely depends on the cost reduction of semiconductor devices and LSI technologies. The proposed algorthm can be realized using only two digital filters and does not require product modulators or Fast Fourier Transform (FFT) processors. The required number of multiplications, which is closely related to the quantity of hardware, is considerably reduced by the multistage structure of this algorithm. The reduction in the kind of required digital hardware and the required number of multiplications makes it possible to efficiently utilize the new hardware realization techniques of digital filters or multipliers using read-only memories and simple logic devices. Since it is foreseen that cost reduction of memory devices will be more rapid than that of logic devices, the proposed algorithm is expected to be advantageous with regard to cost over existing algorithms where complex multiplier logic is required. The estimation of the computation rate is carried out with reference to a practical case. The computer simulation results are also shown. View full abstract»

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Aims & Scope

IEEE Transactions on Communications focuses on all telecommunications including telephone, telegraphy, facsimile, and point-to-point television by electromagnetic propagation.

 

 

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Meet Our Editors

Editor-in-Chief
Robert Schober
University of British Columbia