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Electron Devices, IEEE Transactions on

Issue 1 • Date Jan 1991

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Displaying Results 1 - 25 of 25
  • VIPMOS-a novel buried injector structure for EPROM applications

    Page(s): 111 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    A buried injector is proposed as a source of electrons for substrate hot electrons injection. To enhance the compatibility with VLSI processing, the buried injector is formed by the local overlap of the n-well and p-well of a retrograde twin-well CMOS process. The injector is activated by means of punchthrough. This mechanism allows the realization of a selective injector without increasing the latchup susceptibility. The p-well profile controls the punchthrough voltage. The high injection probability and efficient electron supply mechanism lead to oxide current densities up to 1.0 Å.×cm-2. Programming times of 10 μs have been measured on nonoptimized cells. The realization of a structure for 5-V-only digital and analog applications is viable. A model of the structure for implementation in a circuit simulator, such as SPICE, is presented View full abstract»

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  • Application of E-beam recrystallization to three-layer image processor fabrication

    Page(s): 47 - 54
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    E-beam recrystallization has been applied to the fabrication of a three-layer processor. The seed structure and the E-beam conditions were successfully optimized so that a large-area SOI as wide as 1 mm was recrystallized without void generation with no damage to underlying devices. The actual SOI area in the device, 850×1100 μm, was recrystallized with one E-beam scan by aligning its position. The three-layer image processor was capable of visual image sensing with a feature outline extraction in a parallel processing manner. Normal operations of the fundamental functions have been confirmed, demonstrating the feasibility of E-beam recrystallization for three-dimensional IC application View full abstract»

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  • Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film

    Page(s): 55 - 60
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    Poly-Si thin-film transistors (TFTs) with channel dimensions (width W, and length L) comparable to or smaller than the grain size of the poly-Si film were fabricated and characterized. The grain size of the poly-Si film was enhanced by Si ion implantation followed by a low-temperature anneal and was typically 1 to 3 μm in diameter. A remarkable improvement was observed in the device characteristics as the channel dimensions decreased to W=L =2 μm. On the other hand, TFTs with submicrometer channel dimensions were characterized by an extremely abrupt switching in their ID versus VGS characteristics. The improvement was attributed to a reduction in the effect of the grain boundaries and to the effect of the device's floating body View full abstract»

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  • Disposable polysilicon LDD spacer technology

    Page(s): 39 - 46
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    An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n+/p+ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n+ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n- and boron p- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V View full abstract»

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  • A comprehensive model for inversion layer hole mobility for simulation of submicrometer MOSFET's

    Page(s): 151 - 159
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    A comprehensive model of effective (average) mobility and local-field mobility for holes in MOSFET inversion layers is presented. The semiempirical equation for effective mobility, coupled with the new local-field mobility model, permits accurate two-dimensional simulation of source-to-drain current in MOSFETs. The model accounts for the dependence of mobility on transverse and longitudinal electric fields, channel doping concentration, fixed interface charge density, and temperature. It accounts not only for the scattering by fixed interface charges, and bulk and surface acoustic phonons, but it also correctly describes screened Coulomb scattering at low effective transverse fields (near threshold) and surface roughness scattering at high effective transverse fields. The model is therefore applicable over a much wider range of conditions compared to earlier reported inversion layer hole mobility models while maintaining a physically based character View full abstract»

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  • Conductivity-type conversion in multiple-implant/multiple-anneal SOI

    Page(s): 61 - 66
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    Results of an investigation of the electrical properties of superficial silicon and epitaxial capping layers grown on multiple-implant/anneal SIMOX and zone melt recrystallization substrates are presented. An unexpected SIMOX conductivity type change (from n to p) was observed in the SIMOX superficial layer, as well as in subsequently grown epi-layers. It is believed that the conductivity-type change is related to the presence of a process-induced acceptor impurity or an impurity (oxygen)-vacancy complex View full abstract»

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  • Moderately doped NMOS (M-LDD)-hot electron and current drive optimization

    Page(s): 121 - 127
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    Short-channel NMOS transistors with moderately doped drain (1014 cm-2), and variable sidewall oxide spacer thickness were fabricated and studied. The sensitivities of hot carrier degradation, current drive capability, and other device parameters to the sidewall spacer thickness were measured and evaluated. The results clearly indicate that a moderately doped drain (M-LDD) provides a stable and well-optimized device, compared to a conventional LDD transistor with substantially lower implant dose. A simple model, explaining the observations, is proposed and discussed View full abstract»

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  • Excess low-frequency noise in PtSi on p-type Si Schottky diodes

    Page(s): 160 - 166
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    The power spectrum for platinum silicide on p-type silicon Schottky diodes has been measured for the diodes available on an infrared focal plane array. A careful experimental technique is used to separate the mutual drift of the array as a whole from the drift of the individual diodes. The power spectrum of the noise associated with the diode appears to be white, even for frequencies below 3.0×10-5 Hz. This result is compared with recent models of 1/f noise. The measurements were made on an infrared camera that used a 160×244 PtSi infrared focal plane array. The data from each pixel were digitized to 12 b (0-4095 ADUs). The digital data were transferred to a Hewlett-Packard series 300 computer via the GPIO bus. The camera operated at 30 frames/s View full abstract»

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  • Overshoot-controlled RLC interconnections

    Page(s): 76 - 87
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    How overshoot in the step response of a circuit involving an RLC line can be controlled using a combination of driver and line resistance that depends on the load capacitance is shown. The no-peak condition or its equivalent is used to relate line parameters to the driver and load impedances. This no-peak condition generalizes the impedance matching customarily used for lossless lines, i.e. it provides an alternative to the traditional choice RD=√ L/C. The results allow improved circuit response without risk of overshoot, for example, by reduction of driver resistance below √L/C for cases where line resistance is unavoidable and/or where load capacitance is not negligible compared to line capacitance. The algebraic formulas derived are more effective than case-by-case numerical simulations for analyzing scaling and technology issues, whether on-chip, or at the packaging, board, or system levels View full abstract»

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  • MOSFET doping profiling

    Page(s): 135 - 140
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    An automated technique was developed for rapid measurement of MOSFET channel doping profiles. The technique is based on the well-known relationship between the device threshold voltage and substrate bias. It uses only DC voltage measurements and is not subject to the limitations of conventional capacitance-voltage (C-V) methods. An operational amplifier feedback circuit is used to determine the threshold voltage automatically as the substrate bias voltage is varied. Doping profiles determined with this technique agree very well with those obtained from C-V and from spreading resistance measurements, as well as with those predicted by SUPREM-3. The devices were fabricated with processes representing two generations of CMOS technology. The doping concentrations, channel implants, and gate oxide thicknesses varied significantly between the two, allowing the assessment of the accuracy of doping profile extraction techniques for devices representing a wide performance range View full abstract»

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  • Non-quasi-static models including all injection levels and DC, AC, and transient emitter crowding in bipolar transistors

    Page(s): 167 - 177
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    Two-dimensional equivalent-circuit models for bipolar junction transistors are systematically derived by solving the continuity equations for DC, AC, and transient excitations. These models take into account carrier propagation delay, all injection levels, as well as exponential doping profiles. They include analytically DC, AC, and transient emitter crowding in a more detailed and accurate manner than previously available. Extensions of the models to accommodate arbitrarily doped and heavily doped quasi-neutral layers and to include energy-gap narrowing due to the electron-hole plasma present at high current density are described. The analysis leads to compact large- and small-signal equivalent-circuit lumped models, suitable for use in circuit simulators such as SPICE. The analytical solutions obtained reveal the two-dimensional distribution of the current and carrier densities in the intrinsic base layer and the onset of emitter crowding. They also provide information for the extraction of the intrinsic base resistance. Several assumptions made in the derivations are assessed by the computer program PISCES. The methods presented apply to both homojunction and heterojunction bipolar transistors View full abstract»

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  • A generalized analytical model for the quantum well injection transit time diode

    Page(s): 14 - 22
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    A generalized small-signal model of the quantum well injection transit time (QWITT) diode derived from the authors' previous large-signal model (see. ibid., vol.35, p.2315-2322, Dec. 1987), which includes not only the carrier space-charge effects but also the velocity transient effects and the carrier diffusion effects is presented. Simple closed forms for the device impedance have been obtained for efficient computation, where only one-dimensional integrations are required. It can be applied to any fashion of time dependence of the velocity transient and diffusivity transient, adopting a Gaussian form for the spatial profile of injected carriers. Using the formulas, the small-signal behavior and the design criteria for the QWITT diode are analyzed. Large-signal impedance of the device can also be estimated by the formulas View full abstract»

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  • New approach to resolution limit and advanced image formation techniques in optical lithography

    Page(s): 67 - 75
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    Practical resolution, the minimum feature size with a depth of focus (DOF) required for LSI fabrication process, is analyzed. Dependence of practical resolution on various factors, such as optical system parameters (exposure wavelength λ, and numerical aperture NA), resist processes, and required DOF, is investigated. It is shown that practical resolution in the sub-halfmicrometer region is not improved, and may even be degraded, with increasing NA. Furthermore, resolution improvement by increasing NA becomes less effective as λ becomes shorter. This means that the high-resolution capability of high-NA/short-wavelength optics cannot be utilized to create fine-pattern LSIs. In order to overcome this limitation, the effectiveness of advanced image formation techniques, the phase-shifting method and the FLEX method, in practical resolution enhancement is investigated. It is experimentally verified, using a phase-shifting mask and the excimer laser stepper, that a pattern feature size less than 0.2 μm can be clearly delineated with sufficient focus latitude. These advanced techniques make it possible to overcome the resolution limitation of conventional optical lithography View full abstract»

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  • Electrical characterization of junctions and bipolar transistors formed with in situ doped low-temperature (800°C) epitaxial silicon

    Page(s): 128 - 134
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    The results of characterization of junctions and bipolar transistors formed with in situ doped low-temperature (800°C) epitaxial silicon are presented. The epitaxial silicon layers were deposited by ultra-low pressure chemical vapor deposition (U-LPCVD) preceded by an in situ Ar sputter clean, which makes possible 800°C fabrication of bipolar transistors. For emitter layer depositions, the U-LPCVD process was plasma enhanced to attain high donor incorporation. Three typical structures of bipolar transistors (A: with epitaxial collector, base, and emitter; B: with epitaxial base and emitter; and C: with epitaxial base) were fabricated and compared in this study. The junction characteristics of the fabricated transistors were also investigated. Functional transistors were obtained for all three structures. Ideality factor of the junctions formed within the epitaxial silicon were near unity (1.01). These results support the claim that the bulk quality of the low-temperature epitaxial silicon is good enough for device application View full abstract»

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  • A high-voltage polysilicon TFT with multigate structures

    Page(s): 95 - 100
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    An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log IDS-VGS characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (VGS<0) operation of the polysilicon TFT causes a large increase of breakdown voltage of the multigate TFT with the result that a nearly equal fraction of drain voltage is applied across the region around each elemental TFT. The breakdown voltage of drain of the fabricated multigate TFT which has five elemental TFTs has been elevated up to 80 V View full abstract»

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  • Experimental analysis of HEMT behavior under low-temperature conditions

    Page(s): 3 - 13
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    An experimental analysis of high-electron-mobility transistor (HEMT) behavior under low-temperature conditions is presented. Specific measurements have been performed to investigate the deep-level trapping effects on basic device characteristics such as carrier concentration, electron mobility in the structure, and access resistances. The influence of the collapse phenomenon on the microwave device parameters completes the knowledge of these parasitic effects. Explanation of mechanisms responsible for the anomalous phenomena and means to suppress them are reported. Microwave parameters measurements demonstrate that HEMTs showing no parasitic collapse effects exhibit improved performance at 77 K. Large improvements of current gain cutoff frequency and noise figure are presented View full abstract»

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  • Thin-film SOI CMOS transistors with p+-polysilicon gates

    Page(s): 32 - 38
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    A comparison is given of the use of p+-polysilicon and n+-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide View full abstract»

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  • An improved Early voltage model for advanced bipolar transistors

    Page(s): 179 - 182
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    An improved Early voltage model reflecting the effect of bias variation is developed. The bias dependencies of the Early voltage are more prominent as the base width of the bipolar transistor decreases. Thus, using the conventional constant Early voltage model can result in considerable errors in modeling the advanced bipolar transistors which possess very thin base region. Comparisons between the present model and the conventional model at different bias conditions support this assertion. SPICE simulations are performed to demonstrate the impact of this study on the small-signal performance of bipolar-transistor integrated circuits View full abstract»

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  • Characterization of ultra-shallow p+-n junction diodes fabricated by 500-eV boron-ion implantation

    Page(s): 28 - 31
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    Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B+ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm2 for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm 2. The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation View full abstract»

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  • Identification of a corner tunneling current component in advanced CMOS-compatible bipolar transistors

    Page(s): 107 - 110
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    A corner tunneling current component in the reverse-biased emitter-base junction of advanced CMOS compatible polysilicon self-aligned bipolar transistors has been identified by measuring base current as a function of temperature, bias voltage, and emitter shape. This current is found to be an excess tunneling current caused by an increase in defect density in the corners of the emitter and gives rise to three-dimensional effects in small-geometry devices. The devices used for this study were selected from batches aimed at optimizing the emitter-base system. For this reason, the starting material was n-type (~1016 cm-3) and provided the collector regions of the transistors. The intrinsic base and lightly doped extrinsic base regions were both implanted at 30 keV to a dose of 1×1013 cm-2. The activation anneal was performed at 1060°C for 20 s in a rapid thermal annealer. Under such conditions, the emitter-base junction is located about 600 Å below the polysilicon-substrate interface View full abstract»

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  • Characterization and implementation of self-aligned TiSi2 in submicrometer CMOS technology

    Page(s): 88 - 94
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    Characterization and process implementation of a self-aligned TiSi 2 in a submicrometer CMOS process are presented. The effects of different in situ sputter etch configurations prior to Ti deposition on silicidation is discussed. It is shown that bridging is not only first RTP time- and temperature-dependent, but also dependent on the Ti(N) overetch time. The C49 to C54-TiSi2 phase transformation is found to be dependent on both the C49-TiSi2 film thickness and the linewidth. A potential degradation phenomenon with high-temperature back-end processing is discussed, and the impact of TiSi2 on specific contact resistance and circuit performance is presented. Thin film analysis was done by Auger electron spectrometry, Rutherford backscattering spectrometry with 2-MeV He+ , transmission electron microscopy, secondary ion mass spectrometry, X-ray diffraction, and X-ray fluorescence spectrometry. Sheet resistance measurements were carried out with a four-point probe View full abstract»

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  • Temperature dependence of dynamic operation in ultra-thin CMOS/SIMOX

    Page(s): 101 - 106
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    Dynamic characteristics of fully depleted ultra-thin film CMOS/SIMOX devices in the range from 50 to 300 K are presented. Discussion is focused on the propagation delay time of CMOS/SIMOX ring oscillators. Using a simple theory, it is shown that the measure propagation delay time is larger than the predicted delay time. Adopting a simple theoretical assumption, it is strongly suggested that the propagation delay time is governed ultimately by the charging and discharging time of the inversion layer in off-to-on and on-to-off processes. The results are corroborated by the fact that fully depleted CMOS/SIMOX operate with extremely small parasitic capacitances View full abstract»

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  • Analog dynamic random-access memory (ADRAM) unit cell implemented using a CCD with feedback

    Page(s): 178 - 179
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    A novel unit cell for analog, dynamic, random-access memory is described. The unit cell is implemented using a charge-coupled device (CCD) and features voltage-in/voltage-out operation with low power. The unit cell is essentially an algorithmic voltage sample-and-hold (S/H) circuit. It is sufficiently compact for imager frame memory application and may also find application in analog neural network circuits View full abstract»

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  • The design and characterization of nonoverlapping super self-aligned BiCMOS technology

    Page(s): 141 - 150
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    An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with Leff=1.1 μm and W n/Wp=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with fT, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated View full abstract»

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  • Mobility profiles in short and narrow GaAs MESFET channels

    Page(s): 23 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    Gate-voltage-dependent mobility profiles in long-, short-, wide-, and narrow-channel WNx-BPLDD (buried p-type buffer lightly doped drain region) GaAs MESFETs have been determined (LG =10, 4, 2, 1, 0.8, 0.5, 0.3 μm, WG=20 μm; WG-100, 40, 20, 10, 4, 2 μm, L G=0.5 μm). The mobility mainly depends on the channel width, while the gate length has much less influence. Thus, using proper gate dimensions the channel mobility can be tuned. The highest drift mobility values agree quite well with the measured Hall mobilities. Mobility profiles of large-area MESFETs are probably degraded by the WN x-gate fabrication process. Injected excess charges at gate length below 0.5 μm distorts the mobility evaluations View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology