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Circuits and Systems, IEEE Transactions on

Issue 5 • Date May 1987

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Displaying Results 1 - 22 of 22
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  • A new contribution to the cluster problem

    Page(s): 546 - 552
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    A heuristic algorithm for solving the cluster problem is presented in this paper. The algorithm exploits both the contour tableau and the newly developed path concept, and does not require the choice of a starting node. Experimental results show that the method is competitive with other published algorithms as far as border size is concerned. Furthermore, resultant fill-in is kept small. View full abstract»

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  • A subsequence approach to interpolation using the FFT

    Page(s): 568 - 570
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    A novel approach to using the FFT for interpolating discrete-time signals is presented. It is shown that the number of arithmetic operations can be reduced by decomposing the interpolated signal into an ordered set of subsequences. An example is included to demonstrate the effectiveness of this approach. View full abstract»

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  • A fast implementation of two-dimensional convolution algorithm for image-processing applications

    Page(s): 577 - 579
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    An implementation of the two-dimensional convolution algorithm that is suitable for image-processing applications is presented. The execution time of the algorithm is shown to be reduced due to an efficient data organization and by taking into account the fact that the pixel values in an image assume a fixed number of discrete levels. View full abstract»

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  • Two-dimensional continued fraction inversion

    Page(s): 580 - 582
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    A computationally simple method is presented for the inversion of a two-dimensional (2-D) continued fraction. The procedure is based on the interpretation of a 2-D continued fraction expansion as a driving point admittance and uses results from the theory of two-port networks. The simplicity and the efficiency of the method are illustrated by two examples. View full abstract»

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  • On the stopband sensitivity of digital filters

    Page(s): 582 - 584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    In contrast to the case of passband. sensitivity, a known criterion for low stopband sensitivity does not exist. In this paper, the relation between the stopband sensitivity of a digital filter and the movement of its transmission zeros with coefficient quantization is investigated. View full abstract»

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  • Comparison of several frequency-domain LMS algorithms

    Page(s): 586 - 588
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    In this letter, we investigate and compare several frequencydomain LMS adaptive algorithms. These are Dentino's LMS (DLMS) algorithm, the Fast LMS (FLMS) algorithm, and the proposed Optimal FLMS (OFLMS) algorithm. Computer simulations are carried out to evaluate these algorithms under different conditions. It is shown that the OFLMS produced excellent results, particularly in the case of colored-noise excitation. View full abstract»

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  • Inverting integrator and active filter applications of composite operational amplifiers

    Page(s): 461 - 470
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    A new approach for extending the useful operating frequency range of linear active networks realized using operational amplifiers (OA's) has been reported [1]. The extension in bandwidth (BW) is achieved by replacing each of the single OA's in the active realization by a suitable composite OA (CNOA) that has been constructed usingNOA's. The use of the CNOA's to realize inverting integrators and active filters is presented here. The considerable performance improvement of these realizations is demonstrated both theoretically and experimentally. Their comparison with state-of-the-art designs is also given. View full abstract»

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  • Switched-capacitor circuits with reduced sensitivity to amplifier gain

    Page(s): 571 - 574
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    A new technique for reducing the effect of finite amplifier gain in switched-capacitor circuits is described. The principle is to perform a preliminary charge transfer operation preceding every desired charge transfer operation, thus obtaining a close approximation of the finite gain error which is stored and subsequently used for correction. This provides excellent suppression of the finite gain effect, independent of the relationship between the clock rate and the signal frequencies. The technique is quite general in nature and can be applied in a wide variety of switchedcapacitor circuits. Its major applications will be in precision analog signal processing circuits like precision amplifiers, A/D and D/A converters, and analog arithmetic building blocks. Simulation studies indicate that this technique has the potential to reduce the amplifier gain requirements in such circuits by one to two orders of magnitude. This would simplify amplifier design and increase the high-frequency capability of these circuits. View full abstract»

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  • Stability analysis of interconnected dynamical systems: Hybrid systems involving operators and difference equations

    Page(s): 533 - 545
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1272 KB)  

    We address the stability analysis of interconnected feedback systems of the type depicted in Fig. 1, which consists of a linear interconnection oflsubsystems. Each subsystem is a feedback system in its own right, consisting of a local plant (which is described by an operatorL_i) and of a digital controller (which is described by a system of difference equations and which includes A/D and D/A converters). We establish conditions for the attractivity, asymptotic stability, asymptotic stability in the large, and boundedness of solutions for such systems. The hypotheses of our results are phrased in terms of the I/O properties of the operatorsL_iand of the entire interconnected system, and in terms of the Lyapunov stability properties of digital controllers described by the indicated difference equations. In all cases, our results allow a stability analysis of complex interconnected systems in terms of the qualitative properties of the simpler free subsystems and in terms of the properties of the system interconnecting structure. The applicability of our results is demonstrated by means of a specific example (Fig. 2). View full abstract»

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  • Conditions for overflow stability of a class of complex biquad digital filters

    Page(s): 471 - 479
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    In digital communication networks, complex biquad recursive filters are increasingly being used in the processing of complex signals. This paper examines the stability properties of a class of complex biquad filters having different overflow nonlinearities. Two new sets of conditions have been derived to ensure asymptotic overflow stability of the complex biquad filter with respect to various admissible classes of input signalsX_{sim c}. The subscriptcrefers to the signal level of the complex input sequences; it is a measure of the degree of input scaling. Whenc = 0, the formulation degenerates to the zero-input stability problem. Using the new stability criteria, various regions of stability in the coefficient plane have been derived as a function of the factorc. The overflow nonlinearities considered include saturation, bit-by-bit inversion, zeroing, and modulo 2 arithmetic. View full abstract»

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  • Binary Petri-net relationships

    Page(s): 565 - 568
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    A full set of equations describing binary Petri-nets is presented in terms of integer algebra. In doing this, an equation is developed that allows for determination of the firing vector in terms of the markings and the input. Because the results are expressed in terms of integer arithmetic rather than Boolean algebra, they allow for extension to other classes of Petri-nets as well as yield ease of programming for Petri-net analysis. View full abstract»

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  • A method for the formulation and solution of circuits composed of switches and linear RLC elements

    Page(s): 496 - 509
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1248 KB)  

    Networks composed of switches(S)and linear RLC elements are formulated by state-space equations in which the switchesSare dealt with as the voltage sourcesV_s ( = 0)for closed switches and current sourcesi_s ( = 0)for open switches. The equation associated with the change of switching combinations (mode change) is modified. The solution of the jump of the state vector which occurs at mode change is made clear in the distribution sense. The invariance of state space under mode change is discussed, and the concept of switch controllability and observability is introduced to solve this problem. View full abstract»

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  • A modified procedure to convert a signal flow graph into its Chan model

    Page(s): 584 - 586
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    A modified procedure is presented to convert a signal flow graph representation (SFG) into the "state-space-like" description introduced by Chan. The algorithm proposed is illustrated by an example. Finally, it is shown that each SFG satisfying two conditions can be converted in this manner. View full abstract»

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  • Design of very low sensitivity low-pass switched-capacitor ladder filters

    Page(s): 524 - 532
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (912 KB)  

    Design techniques are described for very low sensitivity low-pass switched-capacitor (SC) ladder filters whose worst-case sensitivities become zero at some specific frequency points. The proposed techniques are based on time sharing of the circuit elements and on implementing parasitics-compensated SC building blocks. Two design methods are proposed: an approximate design for LDI all-pole low-pass SC ladders and an exact design for bilinear elliptic low-pass SC ladders. The approximation error in the former is practically negligible by suitably choosing the clock frequency. The advantage of this approach is that a very low sensitivity property is achieved together with a small capacitance spread, a small total capacitance, and a small operational-amplifier count. View full abstract»

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  • Modified Ansell's method and testing of very strict Hurwitz polynomials

    Page(s): 559 - 561
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    A new modification to the Ansell's Hermite matrix method for the testing of very strict Hurwitz polynomials is presented. In this modification, the testing at infinite distant points is carried out as an integral part of the testing of the determinant of the Hermite matrix. Hence, the additional 1-D tests required to determine the behavior of the polynomial at infinite distant points are eliminated. View full abstract»

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  • Analysis of a symmetrically stabilized three-phase oscillator and some of its applications

    Page(s): 561 - 565
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    A nonlinearly stabilized three-phase oscillator model is treated in the present work. It is shown analytically and demonstrated by a computer solution of the equations that the oscillator equations possess a relatively large region, where stability of solutions is assured. All trajectories initiating or reaching this region are proved to approach a limit cycle solution. The three variablesx_1, x_2, andx_3, representing the final Stable solution versus time, vary in time in a way similar to that of the three voltages of a balanced three-phase power generating System in steady state. The analysis of the relatively complicated third-order nonlinear system is made possible by transforming the original three-phase variablesx_1, x_2, andx_3to new variables (introduced by Daboul)S, M, andphi. The above oscillator has been applied earlier for the representation of power systems. The present thorough analysis of the model increases the authors' confidence that such representation of power systems is dependable. View full abstract»

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  • Composite operational amplifiers: Generation and finite-gain applications

    Page(s): 449 - 460
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1272 KB)  

    A practical and effective general approach is presented for extending the useful operating frequencies and improving the performance of linear active networks realized using operational amplifiers (OA's). This is achieved by replacing each OA in the active network by a composite operational amplifier (CNOA) constructed usingNOA's. The technique of generating the CNOA's for any givenNis proposed. The realizations employing the CNOA are examined according to a stringent performance criterion satisfying such important properties as extended bandwidth, stability with one- and two-pole OA models, low sensitivity to the components and OA mismatch, and wide dynamic range. Several families of CNOA's, forN = 2, 3,and4, are shown to satisfy ,the suggested performance criterion. In this contribution, the CNOA's applications in inverting, noninverting, and differential finite-gain amplifiers are given and shown theoretically and experimentally to compare favorably with the state-of-the-art realizations using the same number of OA's. Applications of the CNOA in inverting integrator and active filter realizations are presented in a companion contribution [32]. View full abstract»

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  • Design of canonic wave digital filters using Brune and matched 4-port adaptors

    Page(s): 480 - 495
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    In this paper, we present a new derivation of an adaptor for the well-known Brune section. It is shown that finite wordlength binary solutions exist for the Brune adaptor with the canonic number of quantized parameters. Furthermore, by giving up one degree of freedom, a much simplified matched 4-port adaptor (all diagonal elements of the scattering matrix are zero) is derived. It is shown that for a particular termination of the ports, the matched 4-port reduces to the wave digital lattice adaptor. Several examples utilizing matched 4-port adaptors in configurations other than the lattice are presented, all of which show excellent properties as well as being computationally very efficient. View full abstract»

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  • Low-sensitivity realization of switched-capacitor filters

    Page(s): 510 - 523
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    Two low-sensitivity switched-capacitor filter structures implementing the strays-insensitive switched-capacitor biquads are presented. They are based on a generalized multiple-loop-feedback (GMF) topology, which is formed by the combination of the follow-the-leader-feedback (FLF) and inverse follow-the-leader-feedback (IFLF) topologies. Design equations that relate the feedback and feedforward parameters to the discrete-time transfer function are derived for both structures. Sensitivity analyses of the proposed structures as well as of the previously published ones are carried out using Monte Carlo simulations. It was found that the modified GMF structure possesses a lower sensitivity with respect to capacitance ratios. View full abstract»

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  • Software and VLSI algorithms for generalized ranked order filtering

    Page(s): 553 - 559
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB)  

    The threshold decomposition architecture is known to provide a modular and parallel design for ranked order filtering. However, the chip area grows exponentially with the number of bits in the input. In this paper a new architecture which is equivalent to the threshold decomposition is shown to have linear growth in the size of the input words. Filtering is accomplished by a pipelined bit by bit algorithm. Hardware modifications to the filtering scheme are accomplished by changing data paths and the number of cells to be replicated rather than modifying the functions performed by each module. Hardware redundancy to prevent single points of failure can be provided when space for extra modules is available. If external data flow control is provided, the chip can be programmed for many different filtering operations. The basic representation of the generalized rank order filter as a maximum of minimums also provides a fast software implementation and intuitive description of these filters as adaptive rank operations. Because the threshold description is extremely slow on a general-purpose computer, this is essential for investigating new applications of these robust signal and image processing filters. View full abstract»

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  • Design of a flexible power-saving logic circuit for CMOS microprocessors employing power-down/save feature

    Page(s): 575 - 576
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    A logic circuit to achieve significant power savings during the inactive periods of CMOS microprocessors({mu}p's)is presented. The circuit employs the built-in power-down/power-save feature of the{mu}p. View full abstract»

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