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Circuits and Systems, IEEE Transactions on

Issue 11 • Date November 1981

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Displaying Results 1 - 11 of 11
  • Introduction to special issue

    Page(s): 1025 - 1026
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    Freely Available from IEEE
  • Design of testable structures defined by simple loops

    Page(s): 1079 - 1088
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    A methodology is given for generating combinational structures from high-level descriptions (using assignment statements, "if' statements, and single-nested loops) of register-transfer (RT) level operators. The generated structures are cellular, and are interconnected in a tree structure. A general algorithm is given to test cellular tree structures with a test length which grows only linearly with the size of the tree. It is proved that this test length is optimal to within a constant factor. Ways of making the structures self-checking are also indicated. View full abstract»

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  • A hardware approach to self-testing of large programmable logic arrays

    Page(s): 1033 - 1037
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    A hardware technique for testing large programmable arrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allows the testing of a PLA within a number of cycles that is a linear function of the number of inputs and product terms. A8 times 16 times 8PLA is completely tested within 52 cycles; a16 times 48 times 8PLA requires 132 cycles. The test patterns do not depend on the individual personalization of any PLA. So there is no more need of an extensive fault simulation or test pattern computation. The result is a fast efficient built-in test for PLA-macros, the most promising building blocks of VLSI circuits. View full abstract»

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  • Diagnosability of nonlinear circuits and systems-Part II: Dynamical systems

    Page(s): 1103 - 1108
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    A theory for the diagnosability of nonlinear dynamical systems, similar to the one in Part I [1] for memoryless systems, is developed. It is based on an input-output model of the system in a Hilbert space setting. A necessary and sufficient condition for the local diagnosability of the system, which is a rank test on a matrix, is derived. A simple sufficient condition is also derived. It is shown that, for locally diagnosable systems, there exist a finite number of test inputs that are sufficient to diagnose the system. Illustrative examples are presented. View full abstract»

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  • Design for autonomous test

    Page(s): 1070 - 1079
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    A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible. Procedures for reconfiguring the existing registers into modified linear feedback shift registers (LFSR's) which apply the exhaustive (not pseudorandom) test patterns or convert the responses into signatures are described. No fault models or test pattern generation programs are required. A method to modify CMOS circuits so that exhaustive testing can be used even when stuck-open faults must be detected is described. A detailed example using the 74181 ALU is presented. View full abstract»

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  • A design of programmable logic arrays with universal tests

    Page(s): 1027 - 1032
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    In this paper the problem of fault detection in easily testable programmable logic arrays (PLA's) is discussed. The easily testable PLA's will be designed by adding extra logic. These augmented PLA's have the following features: 1) for a PLA withninputs andmcolumns (product terms), there exists a "universal" test set such that the test patterns and responses do not depend on the function of the PLA, but depend only on the size of the PLA (the valuesnandm); 2) the number of tests is of ordern + m. For the augmented PLA's, universal test sets to detect faults in PLA's are presented. The types of faults considered here are single and multiple stuck faults and crosspoint faults in PLA's. Fault location and repair of PLA's are also considered. View full abstract»

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  • Multiple fault testing of large circuits by single fault test sets

    Page(s): 1059 - 1069
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    A general theory is presented in this paper to quantitatively predict the multiple fault coverage capability of single fault detection test sets in combinational circuits. The theory is unique in that it provides greatest lower bounds on the coverage capability of all possible circuits of concern by a simple table-look-up process. All the results known so far in this area are seen to be special cases of the theory. The more important contribution of the theory, however, is seen in its predictions made for reconvergent internal fan-out circuits. Most unexpectedly, the multiple fault coverage of such circuits by single fault test sets is discovered to be extremely precarious. Such results clearly have alarming implications in LSI and VLSI testing. View full abstract»

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  • Diagnosability of nonlinear circuits and systems-Part I: The dc case

    Page(s): 1093 - 1102
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    A theory for the diagnosabilty of nonlinear dc circuits (memoryless systems) is developed. Based on an input-output model, a necessary and sufficient condition for the local diagnosability of the system, which is a rank test on a matrix, is derived. Various ways of reducing the computational complexity of this test are indicated. A sufficient condition for single fault diagnosability, which is much weaker than the necessary and sufficient condition for local diagnosability, is also derived. It is also shown that for diagnosable systems,, it is possible to to pick a finite number of test inputs that are sufficient to diagnose the system. An illustrative example is presented. View full abstract»

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  • New measures of testability and test complexity for linear analog failure analysis

    Page(s): 1088 - 1092
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    The failure analysis of analog electronic systems is characterized by numerous, difficult problems. Assessing the testability and test complexity of a given system is one such problem. In fact, robust, quantitative measures of these important features have not been available to the analog testing community. This paper introduces new measures for both testability and test complexity which: 1) are quantitative, 2) are capable of handling multiple faults, and 3) have a well-defined interpretation. These measures are based upon published results from optimal experiment designs as developed in the discipline of systems identification. Parameter testability is defined in terms of information (in the sense of Fisher) return, while test complexity is functionally related to the experiment time required to achieve specified accuracy with regard to the uncertain parameters of interest. Thus both of the new measures introduced depend, not only upon the specific system at hand, but also upon the experimental conditions used in performing the tests. The results of this approach lead to quantitative measures that have optimality features based upon the Cramer-Rao bound. View full abstract»

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  • Design of easily testable bit-sliced systems

    Page(s): 1046 - 1058
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    Bit-sliced systems are formed by interconnecting identical slices or cells to form a one-dimensional iterative logic array (ILA). This paper presents several design techniques for constructing easily testable bit-sliced systems. Properties of ILA's that simplify their testing are examined. C-testable ILA's, which require a constant number of test patterns independent of the array size, are characterized, and a method for making an arbitrary ILA C-testable is presented. A new testability concept for arrays called I-testability is introduced. I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification. I-testable ILA's are characterized, as well as Cl-testable arrays, which are simultaneously C- and I-testable. A method of making an arbitrary ILA Cl-testable is presented. The application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated. For this purpose a family of easily testable processor slices is described. The design of a self-testing CPU based on I-testing is discussed, and compared with a more conventional self-testing design. View full abstract»

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  • A testable design of iterative logic arrays

    Page(s): 1037 - 1045
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    Testable design of unilateral iterative logic arrays (ILA) of combinational cells under the assumption of a single cell failure is considered. The concepts of one-step testability and one-stepC-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. It is shown that if no directly observable outputs from each cell are available, then it is possible to augment the cell flow table by the addition of a fixed number(leq 4)of columns and a row so that a faulty cell can be located by a test of length proportional tolog_2 p, wherepis the number of cells in the array. However, if directly observable outputs are available from each cell, then the test length is shown to be independent of the array length to locate a faulty cell. A set of simpler sufficient conditions are given for the testability of two-dimensional arrays. It is shown that these conditions ensure that all possible input states can be applied to every cell in an array of arbitrary dimensions. View full abstract»

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