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Circuits and Systems, IEEE Transactions on

Issue 4 • Date Apr 1978

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Displaying Results 1 - 12 of 12
  • Weighting coefficients for certain maximally flat nonrecursive digital filters

    Publication Year: 1978 , Page(s): 234 - 235
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    The weighting coefficients for maximally flat nonrecursive digital ruters have been derived for low-pass filters having equal passband and stopband widths. The solution is in closed form and can be readily evaluated even for large filter order. Asymptotically the coefficients of the finite series expansion converge to the Fourier series coefficients. Hilbert transformers and decimation filters are among the suggested applications for this form of filter. View full abstract»

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  • Design of low-pass maximally flat RC-active filters with multiple real pole: The MURROMAF polynomials

    Publication Year: 1978 , Page(s): 196 - 200
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A new class of low-pass all-pole transfer functions is defined, with maximally flat behavior at the origin. The main feature of this class is the introduction of a multiple real pole, in order to realize RC-active filters by cascading third-order sections and, if necessary, second-order sections. This solution yields a reduction in the number of OA's and, consequently, in power consumption and in SNR. View full abstract»

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  • Some results on two-section generalized FLF active filters

    Publication Year: 1978 , Page(s): 181 - 184
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    This paper presents some results on two-section generalized follow-the-leader-feedback (GFLF) active filters. The results are applicable to the design of geometrically symmetrical bandpass (BP) and band-reject (BR) elliptic-type fiters. An example illustrating sensitivity improve ment and lower pole- Q values required for the sections over the cascade design is also given. View full abstract»

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  • Realization of a nonoriented 2n-terminal communication network

    Publication Year: 1978 , Page(s): 237 - 238
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    First Page of the Article
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  • A grounded constant current source with improved bandwidth

    Publication Year: 1978 , Page(s): 235 - 237
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A grounded constant current source employing a single operational amplifier is discussed. It is shown that improved bandwidth and reduced slew rate limitations are obtained with this circuit. View full abstract»

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  • High-Q selective filters using mechanical resonance of silicon beams

    Publication Year: 1978 , Page(s): 215 - 222
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (920 KB)  

    The theory of integrated high- Q selective filters based on the mechanical resonance of single silicon beams is presented. The method for transfer function calculation is developed, and it is shown that the silicon beam filters have high- Q selective characteristics. A construction procedure based on anisotropic etching of silicon and classical integrated technology is proposed. View full abstract»

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  • Block implementation of recursive digital filters--New structures and properties

    Publication Year: 1978 , Page(s): 200 - 207
    Cited by:  Papers (69)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    Several new structures for the block implementation of HilR digital filters are proposed. The relation between the pole locations of the block structure to that of the original scalar transfer function is derived. A method to obtain the scalar transfer function from a given block structure is described. View full abstract»

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  • Design of signal flow graph (SFG) active filters

    Publication Year: 1978 , Page(s): 185 - 195
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB)  

    A systematic procedure is presented for the design of active filters obtained as operational simulations of LC ladder prototypes. The method is based on the signal-flow graph (SFG) approach, but allows one to obtain the final circuit without ever considering signal-flow graphs. Practical design problems, namely, scaling for maximum dynamic range, stabilizing the reciprocator amplifiers, predistorting the LC prototype to compensate for the parasitic reactances introduced by reciprocators, eliminating the inherent dc offsets, and tuning are solved and illustrated by examples. Complete design and experimental results are given for a twelfth-order bandpass channel bank filter. View full abstract»

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  • Transformation between Foster and Cauer equivalent networks

    Publication Year: 1978 , Page(s): 238 - 239
    Cited by:  Papers (59)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    Explicit expressions for the entries of the T -matrices transforming Foster-lI to equivalent Cauer structures are derived. The results are given in a recursive form column-by-column, starting from the first. View full abstract»

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  • All approach to the two-dimensional placement problem in circuit layout

    Publication Year: 1978 , Page(s): 208 - 214
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    In this paper a new approach to the placement problem is introduced. The main idea is to take advantage of what one can do in linear placement in tackling the two-dimensional placement problem. The method consists of three distinct phases, namely: decomposition, linear placement, and iterative improvement Each is clearly spefled out. Both constructive and iterative algorithms are developed. The complexity of computation is analyzed and the method has been tried with practical examples. Although no general conclusion can be made on the effectiveness of the method, it appears that the method is at least comparable to that described in a recent paper [1]. View full abstract»

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  • Sampling theorems for linear shift-variant systems

    Publication Year: 1978 , Page(s): 228 - 233
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    Sampling theorem concepts are applied to certain classes of linear shift-variant systems. Various sampling theorem characterizations arise from different bandlimiting assumptions on the system input and/or impulse response. In two of the three cases considered, the system output is also bandlimited and can be expressed in a sampling theorem expansion. The discrete characterizations arising from these two cases reduce to an identical computational form that can be evaluated with a generalized Z-transform treatment. The Fourier duals of the sampling theorems, wherein the system is characterized by its frequency rather than impulse response, are also presented. View full abstract»

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  • Optimum LSI implementation for a digital phase-locked loop

    Publication Year: 1978 , Page(s): 222 - 228
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    A logically selective delay of a parallel output shift register can phase lock the input/output waveforms. The calculated precision of the phase-lock is related to the shift register's bit size and clock and input frequencies. This basic idea is extended to multistage (or multilevel) operations. For optimum LSI implementation, a technique is described which minimizes bit size and the delay function logic circuitry for a given precision. The method proves that for high-precision operations the shift register's bit size and the delay selecting logic circuitry are reduced, thus improving operating efficiency. Also discussed is the design tradeoff between level complexity and circuit size. Finally, extension to synchronization application is considered. View full abstract»

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