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Electron Device Letters, IEEE

Issue 10 • Date Oct. 1990

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Displaying Results 1 - 19 of 19
  • Uniform, high-gain AlGaAs/In/sub 0.05/Ga/sub 0.95/As/GaAs P-n-p heterojunction bipolar transistors by dual selective etch process

    Page(s): 425 - 427
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB)  

    AlGaAs/InGaAs/GaAs P-n-p heterojunction bipolar transistors (HBTs) have been fabricated using a dual selective etch process. In this process, a thin AlGaAs surface passivation layer surrounding the emitter is defined by selective etching of the GaAs cap layer. The InGaAs base is then exposed by selective etching of the AlGaAs emitter. The resulting devices were very uniform, with current gain varying by less than +or-10% for a given device size. Current gain at a given emitter current density was independent of device size, with gains of over 200 obtained at current densities above 5*10/sup 4/ A/cm/sup 2/.<> View full abstract»

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  • Negative differential resistance of a delta-doping-induced double-barrier quantum-well diode at room temperature

    Page(s): 428 - 430
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    A resonant-tunneling homojunction diode, which is a delta-doping-induced double-barrier quantum-well (D/sup 3/BQW) diode, is presented. The barrier uses the delta n/sup +/-i- delta p/sup +/-i- delta n/sup +/ structure. The current-voltage characteristics exhibit three sections of negative differential resistance (NDR) phenomena. At low bias, N-type NDR is demonstrated due to the resonant-tunneling effect. At higher bias, another N-type NDR appears due to the heating effect in the high electric field. As the external bias increases further, an S-type NDR is observed. This result is attributed to the impact ionization effect of thermionic electrons, and then trapping of holes in the maxima of the valence bands, resulting in barrier lowering and redistribution of voltage.<> View full abstract»

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  • Velocity saturation in the collector of Si/Ge/sub x/Si/sub 1-x//Si HBT's

    Page(s): 431 - 433
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    The effects of velocity saturation on the unity gain-bandwidth product f/sub t/ and transconductance g/sub m/ of n-p-n and p-n-p heterojunction bipolar transistors (HBTs) with Ge/sub x/Si/sub 1-x/ bases are described and simulated. For the n-p-n device, velocity saturation combined with a valence-band offset at the base-collector junction causes accelerated g/sub m/ and f/sub t/ rolloff for current densities greater than the knee current for the Kirk effect. For the p-n-p device, the g/sub m/ and f/sub t/ are degraded for all current densities. These limitations combine with the limits imposed by dislocation formation due to strain in the pseudomorphic layer to impose constraints on the design of Si/Ge/sub x/Si/sub 1-x//Si HBTs.<> View full abstract»

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  • The reduction of backgating in GaAs MESFETs by impact ionization

    Page(s): 434 - 436
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    The reduction of drain current due to reverse substrate bias in GaAs MESFETs fabricated on EL2-compensated substrates is recovered with the application of sufficient drain bias. The recovery is shown to be due to the compensation of the negative space charge at the channel-substrate interface by holes generated by impact ionization in the MESFET channel. Illumination raises the value of drain bias needed for current recovery due to the requirement of additional hole flux to offset the effects of optically generated electrons on EL2 occupancy. Simulation results show that the channel current becomes independent of substrate bias when the bias value is sufficient to completely delete the p-type surface layer.<> View full abstract»

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  • Impact ionization rates in

    Page(s): 437 - 438
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    Impact ionization rates for electrons and holes in View full abstract»

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  • High efficiency and output power from second- and third-harmonic millimeter-wave InP-TED oscillators at frequencies above 170 GHz

    Page(s): 439 - 441
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    InP TED (transferred electron device) oscillators have been experimentally investigated for frequencies between 170 and 279 GHz. It has been found that output powers of more than 7 and 0.2 mW are possible at 180 and 272 GHz using second- and third-harmonic mode operation, respectively. Conversion efficiencies of more than 13% and 0.3% between fundamental and second harmonic and fundamental and third harmonic, respectively, have been found. The conversion efficiencies are comparable to GaAs TEDs. The output powers, conversion efficiencies, and tuning ranges (more than 22%) are the biggest reported for InP TEDs at these frequencies. The output power at third harmonic was sufficient for supplying a superconducting mixer with local oscillator power.<> View full abstract»

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  • Integration of InGaAsP/InP optoelectronic bistable switches with a function of optical erasing

    Page(s): 442 - 444
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    An OE-PPM (optically erasable photonic parallel memory) that is an array of 10*10 optoelectronic bistable switches with an optical set and reset function has been fabricated successfully, and set and reset operation with light signals has been demonstrated. The switch consists of a heterojunction phototransistor (HPT) and a light-emitting diode (LED), and the reset operation is performed by an additional reset HPT. The minimum reset power is 1.6 mu W at a bias voltage of 0.9 V, and the set power and the dissipation current at the same bias condition are 3.4 mu W and 200 mu A, respectively. These values are thought to be low enough for array operation. A light pulse with a width of 10 ns was able to set or reset the switch, though the set and reset powers were increased to 547 and 406 mu W, respectively. The dominant factor that limits the speed of set and reset operation is thought to be the response time of the HPT.<> View full abstract»

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  • A fundamental limitation for bipolar transistor scaling

    Page(s): 445 - 447
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    A microscopic model of minority-carrier diffusion in a heavily doped emitter is proposed. Monte Carlo simulation demonstrates that statistical fluctuation in the base current is one of the fundamental limitations in high-speed applications of scaled bipolar transistors. For the transistor presently investigated, with 5.0- mu m/sup 2/ emitter area, 0.1- mu m junction depth, 8.5-ps measurement time, and 0.75-V emitter/base bias, the base current deviation is 43%. This sets up the maximum operating frequency for the transistor. More lightly doped emitters (such as for heterojunction bipolar transistors) will relax this limitation, but at a cost of increased contact resistance, especially when poly-emitters are utilized. Increasing the emitter/base bias will also make the base current rate more deterministic, but the other limitations such as power dissipation and contact resistance will become more obvious.<> View full abstract»

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  • Improvement of aluminum-Si contact performance in native-oxide-free processing

    Page(s): 448 - 450
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    The improvement of Al-to-Si contact performance to a low contact resistance of 0.4 mu Omega -cm/sup 2/ and a Schottky junction having an n factor of 1.02 without any thermal treatment has been achieved by a native-oxide-free processing technique. The technique consists of N/sub 2/-gas-sealed wet cleaning using pure water with low dissolved oxygen (20 p.p.b.), wafer transport and loading in an N/sub 2/ environment, and Al deposition by low-energy ion bombardment.<> View full abstract»

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  • Negative resistance element for a static memory cell based on enhanced surface generation (MOS devices)

    Page(s): 451 - 453
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB)  

    A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories.<> View full abstract»

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  • A ferroelectric DRAM cell for high-density NVRAMs

    Page(s): 454 - 456
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    The operation of a ferroelectric DRAM (dynamic random access memory) cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store/recall operations and not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied is less than 17 AA. The resistivity and endurance properties of ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very-high-density NVRAM with practically no read/write cycle limit and at least 10/sup 10/ nonvolatile store/recall cycles.<> View full abstract»

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  • InGaAs/InAlAs/InP collector-up microwave heterojunction bipolar transistors

    Page(s): 457 - 459
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    Collector-up InGaAs/InAlAs/InP heterojunction bipolar transistors (HBTs) were successfully fabricated, and their DC and microwave characteristics measured. High collector current density operation (J/sub c/>30 kA/cm/sup 2/) and high base-emitter junction saturation current density (J/sub 0/>10/sup -7/ A/cm/sup 2/) were achieved. A cutoff frequency of f/sub t/=24 GHz and a maximum frequency of oscillation f/sub max/=20 GHz at a collector current density of J/sub 0/=23 kA/cm/sup 2/ were achieved on a nominal 5- mu m*10- mu m device.<> View full abstract»

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  • Impact of snapback-induced hole injection on gate oxide reliability of N-MOSFETs

    Page(s): 460 - 462
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    N-channel MOSFETs associated with CMOS output driver circuits are often driven deep into snapback during electrostatic discharge (ESD) events. The charge-pumping technique is used to show significant hole trapping in the oxide resulting from snapback bias conditions. Floating-gate measurements verify that significant hole current flows through the oxide during snapback. It is noted that snapback-induced hole injection can dramatically reduce gate oxide charge to breakdown and explains reduced hot-carrier lifetimes after snapback stress. Snapback stress results in oxide damage that is in many ways similar to that found during hot-carrier stress and radiation damage. These long-term reliability concerns limit the maximum allowable snapback current.<> View full abstract»

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  • AlGaAs/GaAs P-n-p HBTs with high maximum frequency of oscillation

    Page(s): 463 - 465
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    An investigation of P-n-p HBTs (heterojunction bipolar transistors) with an f/sub max/ of 39 GHz and an f/sub t/ of 19 GHz is presented. Power-added efficiency of 31% was obtained in an amplifier at 10 GHz. The design of the high-speed AlGaAs/GaAs P-n-p HBTs takes account of the large degeneracy in the heavily n-type GaAs base. This doping-dependent degeneracy can induce gradients in the valence-band edge to improve the base transit time. High injection efficiency can be maintained in spite of the large degeneracy by increasing the aluminum content of the emitter. HBTs with emitter aluminum contents of 40% and 75% are described.<> View full abstract»

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  • Experimental characterization and modeling of electron saturation velocity in MOSFETs inversion layer from 90 to 350 K

    Page(s): 466 - 468
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    From saturation transconductance of devices of 0.25- mu m CMOS technology, the saturation velocity of electrons ( nu /sub sat/) in the inversion layer from 90 to 350 K has been determined. The extracted nu /sub sat/ at 300 K was 7.86*10/sup 6/ cm/s, which is significantly lower than that of bulk silicon ( nu /sub sat-blk/) and has a much weaker temperature dependence. The ratio nu /sub sat-blk// nu /sub sat/ is 1.27 at 300 K, and is increased to 1.68 at 90 K. Consistent values of nu /sub sat/ have been determined for devices of three vastly different MOS technologies, demonstrating the technology independence of nu /sub sat/. The results are useful for developing and testing theoretical carrier transport models, and are of practical importance in estimating the ultimate speed performance of surface MOSFETs. An empirical model for nu /sub sat/ as a function of temperature has also been derived for application in predictive device simulation.<> View full abstract»

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  • Novel properties of a 0.1- mu m-long split-gate MODFET

    Page(s): 469 - 471
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    A MODFET with two 30-nm-long gates (separated by 40 nm) has been fabricated using ultrahigh-resolution electron-beam lithography. The proximity of the two gate fingers along with the ability to independently bias them results in the following features: (a) tunability of the threshold voltage, (b) enhancement of the transconductance, especially at low current levels, (c) reduction in short-channel effects, and (d) high-voltage gain and cutoff frequency.<> View full abstract»

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  • Reconciliation of a hot-electron distribution function with the lucky electron-exponential model in silicon

    Page(s): 472 - 474
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    The lucky-electron-exponential model (LE-EM) has been used with some success to model hot-electron-induced degradation. Examination of the LE-EM shows its exponential form is an approximation to the high-energy tails of Monte-Carlo-generated hot-electron distribution functions (HEDFs). It is also suggested that the proper LE-EM mean-free path lambda for use in calculating MOSFET gate leakage current is approximately 50 AA, while the commonly used value of 78 AA is appropriate for modeling phenomena related to impact ionization.<> View full abstract»

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  • 50-GHz self-aligned silicon bipolar transistors with ion-implanted base profiles

    Page(s): 475 - 477
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    Silicon bipolar transistors having cutoff frequencies from 40 to 50 GHz have been fabricated in a double -polysilicon self-aligned structure using a process which relies on ion implantation for the intrinsic base formation. The devices have nearly ideal DC characteristics, with breakdown voltages adequate for most digital applications. The results demonstrate that the performance limits of conventional implanted technologies are significantly higher than previously thought.<> View full abstract»

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  • Schottky diodes of Au on GaAs/sub 1-x/Sb/sub x//GaAs n-N heterostructures grown by MBE

    Page(s): 478 - 480
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    Au Schottky barrier heights on molecular-beam-epitaxial grown n-GaAs/sub 1-x/Sb/sub x//N-GaAs heterostructures with x up to 0.26 have been studied. It was found that phi /sub bn/=0.9-1.77x+2.89x/sup 2/, or phi /sub bn/ approximately=0.77E/sub g/-0.20 for x<0.26. The pinning position of the Fermi level with respect to the valence-band edge for x<0.26 takes the form of E/sub pin/=-0.52x+0.53 eV, which also appears to be valid for an x value up to 1.0.<> View full abstract»

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