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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 12 • Date Dec 1990

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Displaying Results 1 - 12 of 12
  • A general and flexible switchbox router: CARIOCA

    Publication Year: 1990 , Page(s): 1307 - 1317
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB)  

    A switchbox router utilizing layers is presented. Each net is first partitioned into a set of subnets. This decomposition is driven by the minimum Steiner tree. The construction is then carried out on a step-by-step basis, which allows the system to dynamically take new information on the problem into account. The information is examined by a set of expert systems which decide which subnet should be routed next. This part has been implemented with a blackboard architecture. The router can handle pins that are not on a grid on one set of parallel edges. The program has been implemented in the LISP programming language. Many test cases have been run successfully, and some results, including Burstein's difficult switchbox, are presented View full abstract»

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  • Global routing based on Steiner min-max trees

    Publication Year: 1990 , Page(s): 1318 - 1325
    Cited by:  Papers (35)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    Global routing of multiterminal nets is studied. A novel global router is proposed; each step consists of finding a tree, called a Steiner min-max tree, that is Steiner tree with maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). An O (min{e loglog e, n2}) time algorithm is proposed for obtaining a Steiner min-max tree in a weighted graph with e edges and n vertices. (This result should be contrasted with the NP-completeness of the traditional minimum-length Steiner tree problem). Experimental results on difficult examples, on randomly generated data, on master slice chips, and on benchmark examples from the Physical Design Workshop are included View full abstract»

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  • A neural network design for circuit partitioning

    Publication Year: 1990 , Page(s): 1265 - 1271
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A neural network model is proposed for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with those achieved by the C.M. Fiduccia and R.M. Mattheyses (1982) algorithm. The proposed approach can be implemented in hardware to accelerate time-consuming partitioning procedures View full abstract»

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  • Partitioning logic on graph structures to minimize routing cost

    Publication Year: 1990 , Page(s): 1326 - 1334
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    The problem of partitioning logic onto the vertices of a partition graph G such that the cost of routing the global nets of the partition on the edges of G is minimized is discussed. This is referred to as the min-cost partitioning on a graph (MCPG) problem. The MCPG problem generalizes previously studied partitioning problems, such as classical min-cut, the quadrisection approach, min-cost tree partitioning, and multiple way network partitioning. Some applications of this partitioning model are discussed, a framework for its solution is described, and experimental results are presented View full abstract»

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  • Layer assignment for multichip modules

    Publication Year: 1990 , Page(s): 1272 - 1277
    Cited by:  Papers (39)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    The layer assignment problem that arises in the design of a multichip module, a high-performance compact package for the interconnection of several hundred chips, is studied. The aim is to place each net in a x-y pair of layers, so as to minimize the number of such pairs. An approximation algorithm, running in O(nd) time is presented for minimizing the number of layers, where n is the number of nets and d is the (two-dimensional) density of the problem View full abstract»

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  • Aliasing in signature analysis testing with multiple input shift registers

    Publication Year: 1990 , Page(s): 1344 - 1353
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage View full abstract»

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  • Using functional fault simulation and the difference fault model to estimate implementation fault coverage

    Publication Year: 1990 , Page(s): 1335 - 1343
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    An approach to estimate the fault coverage of the implementation of a VLSI design obtained by fault simulation at the function level is presented. The proposed methodology begins by defining a fault model for the functional level, the difference fault model (DFM), which reflects all of the faults in the implementation level. Functional fault detection is recorded by performing a functional simulation of the design, with faults injected as determined by the DFM. The last step is to use the correspondence between the functional faults (in the DFM) and those of the implementation level to yield an estimate of the implementation fault coverage. The results obtained show a very good correlation between the estimated fault coverage, based on fault simulation at the functional level, and the actual fault coverage obtained by fault simulation on a gate-level implementation View full abstract»

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  • Schematic generation with an expert system

    Publication Year: 1990 , Page(s): 1289 - 1306
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1452 KB)  

    A study of schematic generation by a knowledge-based system (KBS) is reported. Schematics must demonstrate features (continuity of signal flow and logical clustering) of a design while remaining simple (few turns and crossings). Algorithmic and manual techniques deal poorly with the multiple conflicting objectives. A successful switchbox router in a KBS suggested the same approach to schematic generation. Schematic generation in a KBS still needs to be partitioned into subproblems to make is tractable. Subproblems include ordering of symbols and the placement of nets (i.e., routing). The ordering of symbols in the direction of information flow is based on a precedence augmented with a rule-based component which recognizes cycles and breaks them intelligently. A heuristic length-based ordering in the other direction tries to minimize crossings. The KBS paradigm is particularly applicable to the routing steps View full abstract»

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  • Long and short covering edges in combination logic circuits

    Publication Year: 1990 , Page(s): 1245 - 1253
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    The polynomial time algorithm obtained earlier by the authors is extended to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. It is shown how to find, in polynomial time, a minimal cardinality set MinMaxSP for a given combinational logic circuit. Combinational circuit verification is used to verify the sequential circuit delays View full abstract»

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  • A circuit-level simulation model of PNPN devices

    Publication Year: 1990 , Page(s): 1254 - 1264
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    A numerical model of a three-junction device is presented. It allows the simulation of the external characteristics of the PNPN family devices, and in this work the simulation of the gate turn-off thyristor is particularly considered. The reasons that led to the realization of this model are explained by reviewing previous works in this area. The model is based on the Ebers-Moll equations extended to include the three-junction devices, and it is implemented (built-up) in the source code of the SPICE2 circuit simulator. A detailed description of the implementation of the model equations and different tests are reported and discussed. The results are in accordance with the measurements from the devices reported on data sheets and the computation time is sufficiently short View full abstract»

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  • Simulation of a MOS transistor with spatially nonuniform channel parameters

    Publication Year: 1990 , Page(s): 1354 - 1357
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    A simulation technique is described for the MOS transistor with spatially nonuniform channel parameters, such as voltage, channel width, oxide thickness, flatband voltage, and interface state density. The model is one-dimensional and relies on a charge-sheet description of the inversion layer. Simulation results are shown for the case of a transistor with a nonuniform profile of trapped negative charge View full abstract»

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  • A multiple layer contour-based gridless channel router

    Publication Year: 1990 , Page(s): 1278 - 1288
    Cited by:  Papers (3)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (856 KB)  

    An n-layer gridless channel router is presented. Instead of the commonly used grid it uses a set of contours as a routing framework. The contours, together with a set of reserved areas, present short circuits and ensure routability of all nets. A compact routing can be expected, since the framework is a very adequate model of the physical channel. It is shown that this router is also versatile enough to handle the classic vertical constraint problem. The inherent flexibility enables a design rule driven tradeoff between the number of vias, the wire length, and the channel height. The behavior of the algorithm has been investigated for many different channels, including the well-known difficult example and its recent derivatives. Very competitive results have been achieved for channel height and via count View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu