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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Oct. 1990

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Displaying Results 1 - 9 of 9
  • A universal MOSFET mobility degradation model for circuit simulation

    Publication Year: 1990, Page(s):1123 - 1126
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    From the physical insights provided by the universal effective mobility versus effective vertical electric field curve for electrons in MOS inversion layers, a simple general expression for the gate voltage dependence of the effective electron mobility is derived for use in SPICE circuit simulation. This expression is quite accurate over a wide range of channel doping concentrations and gate oxide... View full abstract»

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  • A new approach to the simulation of the coupled point defects and impurity diffusion

    Publication Year: 1990, Page(s):1113 - 1122
    Cited by:  Papers (15)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    A program, named FINDPRO, has been developed which efficiently solves the coupled diffusion of point defects and multiple impurity species in two dimensions, using the finite difference method for space discretization. The program simulates an oxidation process step by interfacing with a boundary element oxidation program. It accounts for the effect of point defect recombination by subtracting the... View full abstract»

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  • Learning redesign knowledge circuit redesign

    Publication Year: 1990, Page(s):1047 - 1062
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1492 KB)

    A learning component that has been incorporated into the transmission line troubleshooting system (TLTS), a knowledge-based system which implements a model for performing redesign, is presented. The model was applied in the domain of redesigning circuits which are laid on printed circuit boards. The knowledge of TLTS is organized in a blackboard architecture. The learning component can form new kn... View full abstract»

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  • A hexagonal array machine for multilayer wire routing

    Publication Year: 1990, Page(s):1096 - 1112
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1364 KB)

    A novel hardware accelerator comprised of several fast processors interconnected in the form of a hexagonal mesh with wraparound connections is proposed. The novelty of the proposed architecture stems from the fact that it is suitable not only for single-layer routing, but also for routing in parallel on multiple layers. A hexagonal machine of dimension √kG, with about 3kG ... View full abstract»

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  • Exploiting communication complexity for multilevel logic synthesis

    Publication Year: 1990, Page(s):1017 - 1027
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    A multilevel logic synthesis technique based on minimizing communication complexity is presented. This approach is believed to be viable because, for many types of circuits, the area needed is dominated by interconnections. By minimizing communication complexity and interconnect, area is reduced. This approach performs especially well for functions that are hierarchically decomposable (e.g., adder... View full abstract»

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  • Acceleration of relaxation-based circuit simulation using a multiprocessor system

    Publication Year: 1990, Page(s):1063 - 1072
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (900 KB)

    Several novel methods for the electrical-level simulation of digital VLSI MOS circuits on a shared-memory multiprocessor system are presented. A novel parallel algorithm, the overlapped phases algorithm, for the efficient simulation of circuits containing feedback loops, is presented. The algorithm is based on data flow scheduling and local relaxation of the feedback loops. A novel method for the ... View full abstract»

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  • A module generator for optimized CMOS buffers

    Publication Year: 1990, Page(s):1028 - 1046
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1336 KB)

    The theory and implementation of a module generator for CMOS buffers are presented. The generator is written in the C language, and outputs optimal buffer designs in respect to a preselected objective function and layout. The user has the choice of minimizing delay, power, and area, or a combination of these, plus the choice of layout configuration. The research concentrates mainly on theoretical ... View full abstract»

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  • Timing verification using statically sensitizable paths

    Publication Year: 1990, Page(s):10723 - 10784
    Cited by:  Papers (46)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1052 KB)

    A new approach to the false path problem in timing verifiers is presented. This approach is based on the modeling of both the logic and timing behavior of a circuit. Using the logic propagation conditions associated with each delay, efficient algorithms have been developed to find statically sensitizable paths. These algorithms simultaneously perform a longest path search and a partial verificatio... View full abstract»

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  • Parallel global routing for standard cells

    Publication Year: 1990, Page(s):1085 - 1095
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1020 KB)

    The potential speedup of a standard cell global router using a general-purpose multiprocessor is investigated. LocusRoute, a global routing algorithm for standard cells, and its parallel implementation are presented. The uniprocessor speed and quality of LocusRoute is comparable to modern global routers. LocusRoute compares favorably with the TimberWolf 5.0 global router and a maze router that sea... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu